FPGA/verilog-ethernet
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verilog-ethernet/syn/quartus_pro
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Alex Forencich 4f1eabab17 Split async FIFO resets
2021-10-13 14:05:13 -07:00
..
axis_async_fifo.sdc
Split async FIFO resets
2021-10-13 14:05:13 -07:00
sync_reset.sdc
Add timing constraints for Quartus Prime Pro
2021-05-18 16:02:36 -07:00