mirror of
https://github.com/alexforencich/verilog-ethernet.git
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118 lines
3.1 KiB
Verilog
118 lines
3.1 KiB
Verilog
/*
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Copyright (c) 2015-2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* 10G Ethernet MAC
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*/
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module eth_mac_10g #
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(
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parameter ENABLE_PADDING = 1,
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parameter ENABLE_DIC = 1,
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parameter MIN_FRAME_LENGTH = 64
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)
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(
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input wire rx_clk,
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input wire rx_rst,
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input wire tx_clk,
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input wire tx_rst,
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/*
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* AXI input
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*/
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input wire [63:0] tx_axis_tdata,
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input wire [7:0] tx_axis_tkeep,
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input wire tx_axis_tvalid,
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output wire tx_axis_tready,
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input wire tx_axis_tlast,
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input wire tx_axis_tuser,
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/*
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* AXI output
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*/
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output wire [63:0] rx_axis_tdata,
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output wire [7:0] rx_axis_tkeep,
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output wire rx_axis_tvalid,
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output wire rx_axis_tlast,
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output wire rx_axis_tuser,
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/*
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* XGMII interface
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*/
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input wire [63:0] xgmii_rxd,
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input wire [7:0] xgmii_rxc,
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output wire [63:0] xgmii_txd,
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output wire [7:0] xgmii_txc,
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/*
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* Status
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*/
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output wire rx_error_bad_frame,
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output wire rx_error_bad_fcs,
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/*
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* Configuration
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*/
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input wire [7:0] ifg_delay
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);
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eth_mac_10g_rx
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eth_mac_10g_rx_inst (
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.clk(rx_clk),
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.rst(rx_rst),
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.xgmii_rxd(xgmii_rxd),
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.xgmii_rxc(xgmii_rxc),
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.output_axis_tdata(rx_axis_tdata),
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.output_axis_tkeep(rx_axis_tkeep),
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.output_axis_tvalid(rx_axis_tvalid),
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.output_axis_tlast(rx_axis_tlast),
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.output_axis_tuser(rx_axis_tuser),
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.error_bad_frame(rx_error_bad_frame),
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.error_bad_fcs(rx_error_bad_fcs)
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);
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eth_mac_10g_tx #(
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.ENABLE_PADDING(ENABLE_PADDING),
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.ENABLE_DIC(ENABLE_DIC),
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.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
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)
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eth_mac_10g_tx_inst (
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.clk(tx_clk),
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.rst(tx_rst),
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.input_axis_tdata(tx_axis_tdata),
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.input_axis_tkeep(tx_axis_tkeep),
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.input_axis_tvalid(tx_axis_tvalid),
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.input_axis_tready(tx_axis_tready),
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.input_axis_tlast(tx_axis_tlast),
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.input_axis_tuser(tx_axis_tuser),
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.xgmii_txd(xgmii_txd),
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.xgmii_txc(xgmii_txc),
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.ifg_delay(ifg_delay)
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);
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endmodule
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