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FPGA
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verilog-ethernet
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https://github.com/alexforencich/verilog-ethernet.git
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2025-01-14 06:43:18 +08:00
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verilog-ethernet
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example
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KC705
/
fpga_gmii
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rtl
History
Alex Forencich
6b18e56cb1
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
..
debounce_switch.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
fpga_core.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
fpga.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
sync_signal.v
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
