FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-02-04 07:13:13 +08:00
Code Issues Projects Releases Wiki Activity
verilog-ethernet/.github/workflows
History
Alex Forencich 5f1ad94041 Update ubuntu version in CI 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-02-13 13:03:06 -08:00
..
regression-tests.yml
Update ubuntu version in CI
2023-02-13 13:03:06 -08:00