FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-02-04 07:13:13 +08:00
Code Issues Projects Releases Wiki Activity
verilog-ethernet/example/Alveo/fpga_25g/fpga_AU200
History
Alex Forencich 1b29a88b18 Rename AU200 to Alveo 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-11-08 11:50:50 -08:00
..
config.tcl
Rename AU200 to Alveo
2023-11-08 11:50:50 -08:00
Makefile
Rename AU200 to Alveo
2023-11-08 11:50:50 -08:00