mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-14 06:43:18 +08:00
103 lines
3.8 KiB
Makefile
103 lines
3.8 KiB
Makefile
# Copyright (c) 2021 Alex Forencich
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
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# of this software and associated documentation files (the "Software"), to deal
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# in the Software without restriction, including without limitation the rights
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# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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# copies of the Software, and to permit persons to whom the Software is
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# furnished to do so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included in
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# all copies or substantial portions of the Software.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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# THE SOFTWARE.
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TOPLEVEL_LANG = verilog
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SIM ?= icarus
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WAVES ?= 0
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COCOTB_HDL_TIMEUNIT = 1ns
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COCOTB_HDL_TIMEPRECISION = 1ps
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DUT = eth_mac_phy_10g
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TOPLEVEL = $(DUT)
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MODULE = test_$(DUT)
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VERILOG_SOURCES += ../../rtl/$(DUT).v
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VERILOG_SOURCES += ../../rtl/$(DUT)_rx.v
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VERILOG_SOURCES += ../../rtl/$(DUT)_tx.v
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VERILOG_SOURCES += ../../rtl/eth_phy_10g_rx_if.v
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VERILOG_SOURCES += ../../rtl/eth_phy_10g_rx_ber_mon.v
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VERILOG_SOURCES += ../../rtl/eth_phy_10g_rx_frame_sync.v
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VERILOG_SOURCES += ../../rtl/eth_phy_10g_rx_watchdog.v
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VERILOG_SOURCES += ../../rtl/eth_phy_10g_tx_if.v
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VERILOG_SOURCES += ../../rtl/axis_baser_rx_64.v
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VERILOG_SOURCES += ../../rtl/axis_baser_tx_64.v
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VERILOG_SOURCES += ../../rtl/lfsr.v
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# module parameters
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export PARAM_DATA_WIDTH := 64
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export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
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export PARAM_HDR_WIDTH := 2
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export PARAM_ENABLE_PADDING := 1
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export PARAM_ENABLE_DIC := 1
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export PARAM_MIN_FRAME_LENGTH := 64
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export PARAM_PTP_PERIOD_NS := 6
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export PARAM_PTP_PERIOD_FNS := 26214
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export PARAM_TX_PTP_TS_ENABLE := 1
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export PARAM_TX_PTP_TS_WIDTH := 96
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export PARAM_TX_PTP_TS_CTRL_IN_TUSER := $(PARAM_TX_PTP_TS_ENABLE)
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export PARAM_TX_PTP_TAG_ENABLE := $(PARAM_TX_PTP_TS_ENABLE)
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export PARAM_TX_PTP_TAG_WIDTH := 16
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export PARAM_RX_PTP_TS_ENABLE := $(PARAM_TX_PTP_TS_ENABLE)
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export PARAM_RX_PTP_TS_WIDTH := 96
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export PARAM_TX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_TX_PTP_TS_ENABLE)),1,$(shell expr $(if $(filter-out 1,$(PARAM_TX_PTP_TAG_ENABLE)),0,$(PARAM_TX_PTP_TAG_WIDTH)) + $(if $(filter-out 1,$(TX_PTP_TS_CTRL_IN_TUSER)),0,1) + 1 ))
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export PARAM_RX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_RX_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_RX_PTP_TS_WIDTH) + 1 ))
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export PARAM_BIT_REVERSE := 0
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export PARAM_SCRAMBLER_DISABLE := 0
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export PARAM_PRBS31_ENABLE := 1
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export PARAM_TX_SERDES_PIPELINE := 2
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export PARAM_RX_SERDES_PIPELINE := 2
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export PARAM_BITSLIP_HIGH_CYCLES := 1
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export PARAM_BITSLIP_LOW_CYCLES := 8
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export PARAM_COUNT_125US := 195
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ifeq ($(SIM), icarus)
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PLUSARGS += -fst
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
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ifeq ($(WAVES), 1)
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VERILOG_SOURCES += iverilog_dump.v
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COMPILE_ARGS += -s iverilog_dump
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endif
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else ifeq ($(SIM), verilator)
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COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
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ifeq ($(WAVES), 1)
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COMPILE_ARGS += --trace-fst
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endif
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endif
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include $(shell cocotb-config --makefiles)/Makefile.sim
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iverilog_dump.v:
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echo 'module iverilog_dump();' > $@
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echo 'initial begin' >> $@
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echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@
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echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@
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echo 'end' >> $@
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echo 'endmodule' >> $@
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clean::
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@rm -rf iverilog_dump.v
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@rm -rf dump.fst $(TOPLEVEL).fst
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