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https://github.com/alexforencich/verilog-ethernet.git
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58 lines
2.1 KiB
Verilog
58 lines
2.1 KiB
Verilog
/*
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Copyright (c) 2016-2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* XGMII control/data deinterleave
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*/
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module xgmii_deinterleave
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(
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input wire [72:0] input_xgmii_dc,
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output wire [63:0] output_xgmii_d,
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output wire [7:0] output_xgmii_c
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);
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assign output_xgmii_d[7:0] = input_xgmii_dc[7:0];
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assign output_xgmii_c[0] = input_xgmii_dc[8];
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assign output_xgmii_d[15:8] = input_xgmii_dc[16:9];
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assign output_xgmii_c[1] = input_xgmii_dc[17];
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assign output_xgmii_d[23:16] = input_xgmii_dc[25:18];
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assign output_xgmii_c[2] = input_xgmii_dc[26];
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assign output_xgmii_d[31:24] = input_xgmii_dc[34:27];
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assign output_xgmii_c[3] = input_xgmii_dc[35];
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assign output_xgmii_d[39:32] = input_xgmii_dc[43:36];
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assign output_xgmii_c[4] = input_xgmii_dc[44];
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assign output_xgmii_d[47:40] = input_xgmii_dc[52:45];
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assign output_xgmii_c[5] = input_xgmii_dc[53];
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assign output_xgmii_d[55:48] = input_xgmii_dc[61:54];
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assign output_xgmii_c[6] = input_xgmii_dc[62];
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assign output_xgmii_d[63:56] = input_xgmii_dc[70:63];
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assign output_xgmii_c[7] = input_xgmii_dc[71];
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endmodule
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