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https://github.com/alexforencich/verilog-ethernet.git
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99 lines
2.5 KiB
Verilog
99 lines
2.5 KiB
Verilog
/*
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Copyright (c) 2015-2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4-Stream Ethernet FCS Generator
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*/
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module axis_eth_fcs
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(
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input wire clk,
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input wire rst,
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/*
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* AXI input
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*/
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input wire [7:0] s_axis_tdata,
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input wire s_axis_tvalid,
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output wire s_axis_tready,
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input wire s_axis_tlast,
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input wire s_axis_tuser,
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/*
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* FCS output
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*/
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output wire [31:0] output_fcs,
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output wire output_fcs_valid
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);
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reg [31:0] crc_state = 32'hFFFFFFFF;
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reg [31:0] fcs_reg = 32'h00000000;
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reg fcs_valid_reg = 1'b0;
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wire [31:0] crc_next;
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assign s_axis_tready = 1;
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assign output_fcs = fcs_reg;
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assign output_fcs_valid = fcs_valid_reg;
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lfsr #(
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.LFSR_WIDTH(32),
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.LFSR_POLY(32'h4c11db7),
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.LFSR_CONFIG("GALOIS"),
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.LFSR_FEED_FORWARD(0),
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.REVERSE(1),
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.DATA_WIDTH(8),
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.STYLE("AUTO")
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)
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eth_crc_8 (
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.data_in(s_axis_tdata),
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.state_in(crc_state),
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.data_out(),
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.state_out(crc_next)
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);
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always @(posedge clk) begin
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if (rst) begin
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crc_state <= 32'hFFFFFFFF;
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fcs_reg <= 32'h00000000;
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fcs_valid_reg <= 1'b0;
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end else begin
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fcs_valid_reg <= 1'b0;
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if (s_axis_tvalid) begin
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if (s_axis_tlast) begin
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crc_state <= 32'hFFFFFFFF;
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fcs_reg <= ~crc_next;
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fcs_valid_reg <= 1'b1;
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end else begin
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crc_state <= crc_next;
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end
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end
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end
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end
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endmodule
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