mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-14 06:43:18 +08:00
386 lines
12 KiB
Python
Executable File
386 lines
12 KiB
Python
Executable File
#!/usr/bin/env python
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"""
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Copyright (c) 2015-2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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from myhdl import *
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import os
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import axis_ep
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module = 'axis_frame_length_adjust'
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testbench = 'test_%s_8' % module
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srcs = []
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srcs.append("../rtl/%s.v" % module)
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srcs.append("%s.v" % testbench)
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src = ' '.join(srcs)
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build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
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def bench():
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# Parameters
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DATA_WIDTH = 8
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KEEP_ENABLE = (DATA_WIDTH>8)
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KEEP_WIDTH = (DATA_WIDTH/8)
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ID_ENABLE = 1
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ID_WIDTH = 8
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DEST_ENABLE = 1
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DEST_WIDTH = 8
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USER_ENABLE = 1
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USER_WIDTH = 1
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# Inputs
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clk = Signal(bool(0))
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rst = Signal(bool(0))
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current_test = Signal(intbv(0)[8:])
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s_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
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s_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
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s_axis_tvalid = Signal(bool(0))
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s_axis_tlast = Signal(bool(0))
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s_axis_tid = Signal(intbv(0)[ID_WIDTH:])
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s_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
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s_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
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m_axis_tready = Signal(bool(0))
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status_ready = Signal(bool(0))
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length_min = Signal(intbv(0)[16:])
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length_max = Signal(intbv(0)[16:])
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# Outputs
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s_axis_tready = Signal(bool(0))
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m_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
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m_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
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m_axis_tvalid = Signal(bool(0))
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m_axis_tlast = Signal(bool(0))
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m_axis_tid = Signal(intbv(0)[ID_WIDTH:])
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m_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
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m_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
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status_valid = Signal(bool(0))
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status_frame_pad = Signal(bool(0))
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status_frame_truncate = Signal(bool(0))
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status_frame_length = Signal(intbv(0)[16:])
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status_frame_original_length = Signal(intbv(0)[16:])
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# sources and sinks
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source_pause = Signal(bool(0))
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sink_pause = Signal(bool(0))
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status_sink_pause = Signal(bool(0))
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source = axis_ep.AXIStreamSource()
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source_logic = source.create_logic(
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clk,
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rst,
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tdata=s_axis_tdata,
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tkeep=s_axis_tkeep,
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tvalid=s_axis_tvalid,
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tready=s_axis_tready,
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tlast=s_axis_tlast,
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tid=s_axis_tid,
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tdest=s_axis_tdest,
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tuser=s_axis_tuser,
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pause=source_pause,
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name='source'
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)
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sink = axis_ep.AXIStreamSink()
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sink_logic = sink.create_logic(
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clk,
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rst,
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tdata=m_axis_tdata,
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tkeep=m_axis_tkeep,
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tvalid=m_axis_tvalid,
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tready=m_axis_tready,
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tlast=m_axis_tlast,
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tid=m_axis_tid,
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tdest=m_axis_tdest,
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tuser=m_axis_tuser,
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pause=sink_pause,
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name='sink'
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)
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status_sink = axis_ep.AXIStreamSink()
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status_sink_logic = status_sink.create_logic(
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clk,
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rst,
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tdata=(status_frame_pad, status_frame_truncate, status_frame_length, status_frame_original_length),
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tvalid=status_valid,
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tready=status_ready,
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pause=status_sink_pause,
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name='status_sink'
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)
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# DUT
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if os.system(build_cmd):
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raise Exception("Error running build command")
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dut = Cosimulation(
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"vvp -m myhdl %s.vvp -lxt2" % testbench,
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clk=clk,
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rst=rst,
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current_test=current_test,
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s_axis_tdata=s_axis_tdata,
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s_axis_tkeep=s_axis_tkeep,
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s_axis_tvalid=s_axis_tvalid,
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s_axis_tready=s_axis_tready,
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s_axis_tlast=s_axis_tlast,
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s_axis_tid=s_axis_tid,
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s_axis_tdest=s_axis_tdest,
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s_axis_tuser=s_axis_tuser,
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m_axis_tdata=m_axis_tdata,
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m_axis_tkeep=m_axis_tkeep,
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m_axis_tvalid=m_axis_tvalid,
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m_axis_tready=m_axis_tready,
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m_axis_tlast=m_axis_tlast,
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m_axis_tid=m_axis_tid,
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m_axis_tdest=m_axis_tdest,
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m_axis_tuser=m_axis_tuser,
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status_valid=status_valid,
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status_ready=status_ready,
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status_frame_pad=status_frame_pad,
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status_frame_truncate=status_frame_truncate,
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status_frame_length=status_frame_length,
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status_frame_original_length=status_frame_original_length,
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length_min=length_min,
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length_max=length_max
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)
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@always(delay(4))
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def clkgen():
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clk.next = not clk
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def wait_normal():
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while s_axis_tvalid or m_axis_tvalid:
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yield clk.posedge
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def wait_pause_source():
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while s_axis_tvalid or m_axis_tvalid:
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yield clk.posedge
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yield clk.posedge
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source_pause.next = False
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yield clk.posedge
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source_pause.next = True
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yield clk.posedge
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source_pause.next = False
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def wait_pause_sink():
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while s_axis_tvalid or m_axis_tvalid:
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sink_pause.next = True
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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sink_pause.next = False
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yield clk.posedge
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@instance
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def check():
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yield delay(100)
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yield clk.posedge
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rst.next = 1
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yield clk.posedge
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rst.next = 0
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yield clk.posedge
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yield delay(100)
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yield clk.posedge
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length_min.next = 1
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length_max.next = 20
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for lmax in range(1,6):
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for lmin in range(0,lmax+1):
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length_min.next = lmin
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length_max.next = lmax
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for payload_len in range(1,6):
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yield clk.posedge
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print("test 1: test packet, length %d" % payload_len)
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current_test.next = 1
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test_frame = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=1, dest=1)
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for wait in wait_normal, wait_pause_source, wait_pause_sink:
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source.send(test_frame)
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yield clk.posedge
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yield clk.posedge
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yield wait()
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yield sink.wait()
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rx_frame = sink.recv()
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lrx = len(rx_frame.data)
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lt = len(test_frame.data)
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lm = min(lrx, lt)
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assert lrx >= lmin
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assert lrx <= lmax
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assert rx_frame.data[:lm] == test_frame.data[:lm]
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yield status_sink.wait()
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status = status_sink.recv()
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assert status.data[0][0] == (lt < lmin)
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assert status.data[0][1] == (lt > lmax)
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assert status.data[0][2] == lrx
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assert status.data[0][3] == lt
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assert sink.empty()
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assert status_sink.empty()
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yield delay(100)
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yield clk.posedge
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print("test 2: back-to-back packets, length %d" % payload_len)
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current_test.next = 2
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test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=2, dest=1)
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test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=2, dest=2)
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for wait in wait_normal, wait_pause_source, wait_pause_sink:
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source.send(test_frame1)
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source.send(test_frame2)
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yield clk.posedge
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yield clk.posedge
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yield wait()
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yield sink.wait()
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rx_frame = sink.recv()
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lrx = len(rx_frame.data)
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lt = len(test_frame1.data)
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lm = min(lrx, lt)
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assert lrx >= lmin
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assert lrx <= lmax
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assert rx_frame.data[:lm] == test_frame1.data[:lm]
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yield status_sink.wait()
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status = status_sink.recv()
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assert status.data[0][0] == (lt < lmin)
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assert status.data[0][1] == (lt > lmax)
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assert status.data[0][2] == lrx
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assert status.data[0][3] == lt
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yield sink.wait()
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rx_frame = sink.recv()
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lrx = len(rx_frame.data)
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lt = len(test_frame2.data)
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lm = min(lrx, lt)
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assert lrx >= lmin
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assert lrx <= lmax
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assert rx_frame.data[:lm] == test_frame2.data[:lm]
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yield status_sink.wait()
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status = status_sink.recv()
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assert status.data[0][0] == (lt < lmin)
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assert status.data[0][1] == (lt > lmax)
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assert status.data[0][2] == lrx
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assert status.data[0][3] == lt
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assert sink.empty()
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assert status_sink.empty()
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yield delay(100)
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yield clk.posedge
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print("test 3: tuser assert, length %d" % payload_len)
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current_test.next = 3
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test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=3, dest=1)
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test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=3, dest=2)
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test_frame1.last_cycle_user = 1
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for wait in wait_normal, wait_pause_source, wait_pause_sink:
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source.send(test_frame1)
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source.send(test_frame2)
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yield clk.posedge
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yield clk.posedge
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yield wait()
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yield sink.wait()
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rx_frame = sink.recv()
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lrx = len(rx_frame.data)
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lt = len(test_frame1.data)
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lm = min(lrx, lt)
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assert lrx >= lmin
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assert lrx <= lmax
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assert rx_frame.data[:lm] == test_frame1.data[:lm]
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assert rx_frame.last_cycle_user
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yield status_sink.wait()
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status = status_sink.recv()
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assert status.data[0][0] == (lt < lmin)
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assert status.data[0][1] == (lt > lmax)
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assert status.data[0][2] == lrx
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assert status.data[0][3] == lt
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yield sink.wait()
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rx_frame = sink.recv()
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lrx = len(rx_frame.data)
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lt = len(test_frame2.data)
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lm = min(lrx, lt)
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assert lrx >= lmin
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assert lrx <= lmax
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assert rx_frame.data[:lm] == test_frame2.data[:lm]
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yield status_sink.wait()
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status = status_sink.recv()
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assert status.data[0][0] == (lt < lmin)
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assert status.data[0][1] == (lt > lmax)
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assert status.data[0][2] == lrx
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assert status.data[0][3] == lt
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assert sink.empty()
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assert status_sink.empty()
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yield delay(100)
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raise StopSimulation
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return instances()
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def test_bench():
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os.chdir(os.path.dirname(os.path.abspath(__file__)))
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sim = Simulation(bench())
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sim.run()
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if __name__ == '__main__':
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print("Running test...")
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test_bench()
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