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https://github.com/alexforencich/verilog-ethernet.git
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116 lines
3.4 KiB
Verilog
116 lines
3.4 KiB
Verilog
/*
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Copyright (c) 2019 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4-Stream frame length measurement
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*/
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module axis_frame_len #
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(
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// Width of AXI stream interfaces in bits
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parameter DATA_WIDTH = 64,
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// Propagate tkeep signal
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// If disabled, tkeep assumed to be 1'b1
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parameter KEEP_ENABLE = (DATA_WIDTH>8),
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// tkeep signal width (words per cycle)
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parameter KEEP_WIDTH = (DATA_WIDTH/8),
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// Width of length counter
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parameter LEN_WIDTH = 16
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI monitor
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*/
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input wire [KEEP_WIDTH-1:0] monitor_axis_tkeep,
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input wire monitor_axis_tvalid,
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input wire monitor_axis_tready,
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input wire monitor_axis_tlast,
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/*
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* Status
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*/
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output wire [LEN_WIDTH-1:0] frame_len,
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output wire frame_len_valid
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);
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reg [LEN_WIDTH-1:0] frame_len_reg = 0, frame_len_next;
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reg frame_len_valid_reg = 1'b0, frame_len_valid_next;
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reg frame_reg = 1'b0, frame_next;
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assign frame_len = frame_len_reg;
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assign frame_len_valid = frame_len_valid_reg;
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integer offset, i, bit_cnt;
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always @* begin
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frame_len_next = frame_len_reg;
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frame_len_valid_next = 1'b0;
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frame_next = frame_reg;
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if (monitor_axis_tready && monitor_axis_tvalid) begin
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// valid transfer cycle
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if (monitor_axis_tlast) begin
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// end of frame
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frame_len_valid_next = 1'b1;
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frame_next = 1'b0;
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end else if (!frame_reg) begin
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// first word after end of frame
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frame_len_next = 0;
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frame_next = 1'b1;
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end
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// increment frame length by number of words transferred
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if (KEEP_ENABLE) begin
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bit_cnt = 0;
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for (i = 0; i <= KEEP_WIDTH; i = i + 1) begin
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if (monitor_axis_tkeep == ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-i)) bit_cnt = i;
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end
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frame_len_next = frame_len_next + bit_cnt;
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end else begin
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frame_len_next = frame_len_next + 1;
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end
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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frame_len_reg <= 0;
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frame_len_valid_reg <= 0;
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frame_reg <= 1'b0;
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end else begin
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frame_len_reg <= frame_len_next;
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frame_len_valid_reg <= frame_len_valid_next;
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frame_reg <= frame_next;
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end
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end
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endmodule
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