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verilog-ethernet
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Alex Forencich
fd1ec1690f
Add sync_reset module and timing constraints
2020-03-27 18:04:04 -07:00
..
axis_async_fifo.tcl
Add false path for async FIFO implementation in distributed RAM
2019-06-10 17:40:30 -07:00
sync_reset.tcl
Add sync_reset module and timing constraints
2020-03-27 18:04:04 -07:00