FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-02-04 07:13:13 +08:00
Code Issues Projects Releases Wiki Activity
verilog-ethernet/example/HTG9200
History
Alex Forencich 4a65e3594c Connect all PLL control lines on HTG-9200 board 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-07-20 01:17:49 -07:00
..
fpga_25g
Connect all PLL control lines on HTG-9200 board
2023-07-20 01:17:49 -07:00