FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-02-04 07:13:13 +08:00
Code Issues Projects Releases Wiki Activity
verilog-ethernet/example/DE5-Net/fpga/rtl
History
Alex Forencich 27ed447005 Use common sync_reset module files
2020-03-27 18:27:45 -07:00
..
debounce_switch.v
Happy new year
2018-02-26 12:50:51 -08:00
fpga_core.v
Parametrize Ethernet frame parsing
2020-02-21 21:37:57 -08:00
fpga.v
Use common sync_reset module files
2020-03-27 18:27:45 -07:00
i2c_master.v
Happy new year
2018-02-26 12:50:51 -08:00
si570_i2c_init.v
Happy new year
2018-02-26 12:50:51 -08:00
sync_signal.v
Happy new year
2018-02-26 12:50:51 -08:00