mirror of
https://github.com/alexforencich/verilog-ethernet.git
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455 lines
18 KiB
Verilog
455 lines
18 KiB
Verilog
/*
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Copyright (c) 2014 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4-Stream ethernet frame transmitter (Ethernet frame in, AXI out, 64 bit datapath)
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*/
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module eth_axis_tx_64
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(
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input wire clk,
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input wire rst,
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/*
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* Ethernet frame input
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*/
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input wire input_eth_hdr_valid,
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output wire input_eth_hdr_ready,
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input wire [47:0] input_eth_dest_mac,
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input wire [47:0] input_eth_src_mac,
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input wire [15:0] input_eth_type,
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input wire [63:0] input_eth_payload_tdata,
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input wire [7:0] input_eth_payload_tkeep,
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input wire input_eth_payload_tvalid,
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output wire input_eth_payload_tready,
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input wire input_eth_payload_tlast,
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input wire input_eth_payload_tuser,
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/*
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* AXI output
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*/
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output wire [63:0] output_axis_tdata,
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output wire [7:0] output_axis_tkeep,
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output wire output_axis_tvalid,
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input wire output_axis_tready,
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output wire output_axis_tlast,
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output wire output_axis_tuser,
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/*
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* Status signals
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*/
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output wire busy
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);
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/*
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Ethernet frame
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Field Length
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Destination MAC address 6 octets
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Source MAC address 6 octets
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Ethertype 2 octets
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This module receives an Ethernet frame with parallel field input
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and an AXI interface for the payload data and produces an AXI
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output stream.
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*/
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localparam [2:0]
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STATE_IDLE = 3'd0,
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STATE_WRITE_HEADER = 3'd1,
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STATE_WRITE_HEADER_LAST = 3'd2,
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STATE_WRITE_HEADER_LAST_WAIT = 3'd3,
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STATE_WRITE_PAYLOAD_IDLE = 3'd4,
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STATE_WRITE_PAYLOAD_TRANSFER = 3'd5,
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STATE_WRITE_PAYLOAD_TRANSFER_WAIT = 3'd6,
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STATE_WRITE_PAYLOAD_TRANSFER_LAST = 3'd7;
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reg [2:0] state_reg = STATE_IDLE, state_next;
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// datapath control signals
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reg store_eth_hdr;
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reg [63:0] write_hdr_data;
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reg [7:0] write_hdr_keep;
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reg write_hdr_out;
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reg write_hdr_temp;
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reg transfer_in_save;
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reg transfer_save_out;
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reg transfer_in_out;
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reg transfer_in_temp;
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reg transfer_temp_out;
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reg [7:0] frame_ptr_reg = 0, frame_ptr_next;
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reg [47:0] eth_dest_mac_reg = 0;
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reg [47:0] eth_src_mac_reg = 0;
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reg [15:0] eth_type_reg = 0;
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reg input_eth_hdr_ready_reg = 0;
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reg input_eth_payload_tready_reg = 0;
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reg [63:0] output_axis_tdata_reg = 0;
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reg [7:0] output_axis_tkeep_reg = 0;
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reg output_axis_tvalid_reg = 0;
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reg output_axis_tlast_reg = 0;
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reg output_axis_tuser_reg = 0;
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reg busy_reg = 0;
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reg [63:0] temp_axis_tdata_reg = 0;
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reg [7:0] temp_axis_tkeep_reg = 0;
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reg temp_axis_tlast_reg = 0;
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reg temp_axis_tuser_reg = 0;
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reg [63:0] save_eth_payload_tdata_reg = 0;
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reg [7:0] save_eth_payload_tkeep_reg = 0;
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reg save_eth_payload_tlast_reg = 0;
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reg save_eth_payload_tuser_reg = 0;
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assign input_eth_hdr_ready = input_eth_hdr_ready_reg;
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assign input_eth_payload_tready = input_eth_payload_tready_reg;
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assign output_axis_tdata = output_axis_tdata_reg;
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assign output_axis_tkeep = output_axis_tkeep_reg;
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assign output_axis_tvalid = output_axis_tvalid_reg;
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assign output_axis_tlast = output_axis_tlast_reg;
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assign output_axis_tuser = output_axis_tuser_reg;
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assign busy = busy_reg;
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always @* begin
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state_next = 2'bz;
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store_eth_hdr = 0;
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write_hdr_data = 0;
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write_hdr_keep = 0;
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write_hdr_out = 0;
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write_hdr_temp = 0;
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transfer_in_save = 0;
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transfer_save_out = 0;
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transfer_in_out = 0;
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transfer_in_temp = 0;
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transfer_temp_out = 0;
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frame_ptr_next = frame_ptr_reg;
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case (state_reg)
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STATE_IDLE: begin
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// idle state - wait for data
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frame_ptr_next = 0;
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if (input_eth_hdr_valid) begin
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store_eth_hdr = 1;
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write_hdr_out = 1;
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write_hdr_data[ 7: 0] = input_eth_dest_mac[47:40];
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write_hdr_data[15: 8] = input_eth_dest_mac[39:32];
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write_hdr_data[23:16] = input_eth_dest_mac[31:24];
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write_hdr_data[31:24] = input_eth_dest_mac[23:16];
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write_hdr_data[39:32] = input_eth_dest_mac[15: 8];
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write_hdr_data[47:40] = input_eth_dest_mac[ 7: 0];
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write_hdr_data[55:48] = input_eth_src_mac[47:40];
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write_hdr_data[63:56] = input_eth_src_mac[39:32];
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write_hdr_keep = 8'hff;
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frame_ptr_next = 8;
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state_next = STATE_WRITE_HEADER_LAST;
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end else begin
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state_next = STATE_IDLE;
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end
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end
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STATE_WRITE_HEADER_LAST: begin
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// last header word requires first payload word; process accordingly
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if (input_eth_payload_tvalid & output_axis_tready) begin
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// word transfer through - update output register
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transfer_in_save = 1;
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write_hdr_out = 1;
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write_hdr_data[ 7: 0] = eth_src_mac_reg[31:24];
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write_hdr_data[15: 8] = eth_src_mac_reg[23:16];
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write_hdr_data[23:16] = eth_src_mac_reg[15: 8];
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write_hdr_data[31:24] = eth_src_mac_reg[ 7: 0];
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write_hdr_data[39:32] = eth_type_reg[15: 8];
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write_hdr_data[47:40] = eth_type_reg[ 7: 0];
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write_hdr_data[55:48] = input_eth_payload_tdata[ 7: 0];
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write_hdr_data[63:56] = input_eth_payload_tdata[15: 8];
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write_hdr_keep = {input_eth_payload_tkeep[1:0], 6'h3F};
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if (input_eth_payload_tlast) begin
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state_next = STATE_WRITE_PAYLOAD_TRANSFER_LAST;
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end else begin
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state_next = STATE_WRITE_PAYLOAD_TRANSFER;
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end
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end else if (~input_eth_payload_tvalid & output_axis_tready) begin
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// word transfer out - go back to idle
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state_next = STATE_WRITE_HEADER_LAST_WAIT;
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end else if (input_eth_payload_tvalid & ~output_axis_tready) begin
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// word transfer in - store in temp
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transfer_in_save = 1;
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write_hdr_temp = 1;
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write_hdr_data[ 7: 0] = eth_src_mac_reg[31:24];
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write_hdr_data[15: 8] = eth_src_mac_reg[23:16];
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write_hdr_data[23:16] = eth_src_mac_reg[15: 8];
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write_hdr_data[31:24] = eth_src_mac_reg[ 7: 0];
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write_hdr_data[39:32] = eth_type_reg[15: 8];
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write_hdr_data[47:40] = eth_type_reg[ 7: 0];
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write_hdr_data[55:48] = input_eth_payload_tdata[ 7: 0];
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write_hdr_data[63:56] = input_eth_payload_tdata[15: 8];
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write_hdr_keep = {input_eth_payload_tkeep[1:0], 6'h3F};
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state_next = STATE_WRITE_PAYLOAD_TRANSFER_WAIT;
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end else begin
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state_next = STATE_WRITE_PAYLOAD_TRANSFER;
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end
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end
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STATE_WRITE_HEADER_LAST_WAIT: begin
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// last header word requires first payload word; no data in registers
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if (input_eth_payload_tvalid) begin
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// word transfer in - store it in output register
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transfer_in_save = 1;
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write_hdr_out = 1;
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write_hdr_data[ 7: 0] = eth_src_mac_reg[31:24];
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write_hdr_data[15: 8] = eth_src_mac_reg[23:16];
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write_hdr_data[23:16] = eth_src_mac_reg[15: 8];
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write_hdr_data[31:24] = eth_src_mac_reg[ 7: 0];
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write_hdr_data[39:32] = eth_type_reg[15: 8];
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write_hdr_data[47:40] = eth_type_reg[ 7: 0];
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write_hdr_data[55:48] = input_eth_payload_tdata[ 7: 0];
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write_hdr_data[63:56] = input_eth_payload_tdata[15: 8];
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write_hdr_keep = {input_eth_payload_tkeep[1:0], 6'h3F};
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if (input_eth_payload_tlast) begin
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state_next = STATE_WRITE_PAYLOAD_TRANSFER_LAST;
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end else begin
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state_next = STATE_WRITE_PAYLOAD_TRANSFER;
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end
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end else begin
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state_next = STATE_WRITE_HEADER_LAST_WAIT;
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end
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end
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STATE_WRITE_PAYLOAD_IDLE: begin
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// idle; no data in registers
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if (input_eth_payload_tvalid) begin
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// word transfer in - store it in output register
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transfer_in_save = 1;
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transfer_in_out = 1;
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if (input_eth_payload_tlast) begin
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state_next = STATE_WRITE_PAYLOAD_TRANSFER_LAST;
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end else begin
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state_next = STATE_WRITE_PAYLOAD_TRANSFER;
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end
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end else begin
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state_next = STATE_WRITE_PAYLOAD_IDLE;
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end
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end
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STATE_WRITE_PAYLOAD_TRANSFER: begin
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// write payload; data in output register
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if (input_eth_payload_tvalid & output_axis_tready) begin
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// word transfer through - update output register
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transfer_in_save = 1;
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transfer_in_out = 1;
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if (input_eth_payload_tlast) begin
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state_next = STATE_WRITE_PAYLOAD_TRANSFER_LAST;
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end else begin
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state_next = STATE_WRITE_PAYLOAD_TRANSFER;
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end
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end else if (~input_eth_payload_tvalid & output_axis_tready) begin
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// word transfer out - go back to idle
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state_next = STATE_WRITE_PAYLOAD_IDLE;
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end else if (input_eth_payload_tvalid & ~output_axis_tready) begin
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// word transfer in - store in temp
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transfer_in_save = 1;
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transfer_in_temp = 1;
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state_next = STATE_WRITE_PAYLOAD_TRANSFER_WAIT;
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end else begin
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state_next = STATE_WRITE_PAYLOAD_TRANSFER;
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end
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end
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STATE_WRITE_PAYLOAD_TRANSFER_WAIT: begin
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// write payload; data in both output and temp registers
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if (output_axis_tready) begin
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// transfer out - move temp to output
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transfer_temp_out = 1;
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if (temp_axis_tlast_reg | (save_eth_payload_tlast_reg & save_eth_payload_tkeep_reg[7:6] != 0)) begin
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state_next = STATE_WRITE_PAYLOAD_TRANSFER_LAST;
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end else begin
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state_next = STATE_WRITE_PAYLOAD_TRANSFER;
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end
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end else begin
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state_next = STATE_WRITE_PAYLOAD_TRANSFER_WAIT;
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end
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end
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STATE_WRITE_PAYLOAD_TRANSFER_LAST: begin
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// write last payload word; data in output register; do not accept new data
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if (output_axis_tready) begin
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// word transfer out - done
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if (save_eth_payload_tkeep_reg[7:2]) begin
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// part of word in save register
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transfer_save_out = 1;
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state_next = STATE_WRITE_PAYLOAD_TRANSFER_LAST;
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end else begin
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// nothing in save register; done
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state_next = STATE_IDLE;
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end
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end else begin
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state_next = STATE_WRITE_PAYLOAD_TRANSFER_LAST;
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end
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end
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endcase
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end
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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state_reg <= STATE_IDLE;
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frame_ptr_reg <= 0;
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input_eth_hdr_ready_reg <= 0;
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input_eth_payload_tready_reg <= 0;
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eth_dest_mac_reg <= 0;
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eth_src_mac_reg <= 0;
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eth_type_reg <= 0;
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output_axis_tdata_reg <= 0;
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output_axis_tkeep_reg <= 0;
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output_axis_tvalid_reg <= 0;
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output_axis_tlast_reg <= 0;
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output_axis_tuser_reg <= 0;
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temp_axis_tdata_reg <= 0;
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temp_axis_tkeep_reg <= 0;
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temp_axis_tlast_reg <= 0;
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temp_axis_tuser_reg <= 0;
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save_eth_payload_tdata_reg <= 0;
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save_eth_payload_tkeep_reg <= 0;
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save_eth_payload_tlast_reg <= 0;
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save_eth_payload_tuser_reg <= 0;
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busy_reg <= 0;
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end else begin
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state_reg <= state_next;
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frame_ptr_reg <= frame_ptr_next;
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busy_reg <= state_next != STATE_IDLE;
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// generate valid outputs
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case (state_next)
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STATE_IDLE: begin
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// idle; accept new data
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input_eth_hdr_ready_reg <= 1;
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input_eth_payload_tready_reg <= 0;
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output_axis_tvalid_reg <= 0;
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end
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STATE_WRITE_HEADER: begin
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// read header; accept new data
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input_eth_hdr_ready_reg <= 0;
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input_eth_payload_tready_reg <= 0;
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output_axis_tvalid_reg <= 1;
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end
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STATE_WRITE_HEADER_LAST: begin
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// write last header word; need first data word
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input_eth_hdr_ready_reg <= 0;
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input_eth_payload_tready_reg <= 1;
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output_axis_tvalid_reg <= 1;
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end
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STATE_WRITE_HEADER_LAST_WAIT: begin
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// last header word requires first payload word; no data in registers
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input_eth_hdr_ready_reg <= 0;
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input_eth_payload_tready_reg <= 1;
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output_axis_tvalid_reg <= 0;
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end
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STATE_WRITE_PAYLOAD_IDLE: begin
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// write payload; no data in registers; accept new data
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input_eth_hdr_ready_reg <= 0;
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input_eth_payload_tready_reg <= 1;
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output_axis_tvalid_reg <= 0;
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end
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STATE_WRITE_PAYLOAD_TRANSFER: begin
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// write payload; data in output register; accept new data
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input_eth_hdr_ready_reg <= 0;
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input_eth_payload_tready_reg <= 1;
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output_axis_tvalid_reg <= 1;
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end
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STATE_WRITE_PAYLOAD_TRANSFER_WAIT: begin
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// write payload; data in output and temp registers; do not accept new data
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input_eth_hdr_ready_reg <= 0;
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input_eth_payload_tready_reg <= 0;
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output_axis_tvalid_reg <= 1;
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end
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STATE_WRITE_PAYLOAD_TRANSFER_LAST: begin
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// write last payload word; data in output register; do not accept new data
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input_eth_hdr_ready_reg <= 0;
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input_eth_payload_tready_reg <= 0;
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output_axis_tvalid_reg <= 1;
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end
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endcase
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if (store_eth_hdr) begin
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eth_dest_mac_reg <= input_eth_dest_mac;
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eth_src_mac_reg <= input_eth_src_mac;
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eth_type_reg <= input_eth_type;
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end
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if (transfer_in_save) begin
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save_eth_payload_tdata_reg <= input_eth_payload_tdata;
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save_eth_payload_tkeep_reg <= input_eth_payload_tkeep;
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save_eth_payload_tlast_reg <= input_eth_payload_tlast;
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save_eth_payload_tuser_reg <= input_eth_payload_tuser;
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end else if (transfer_save_out) begin
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output_axis_tdata_reg <= {16'd0, save_eth_payload_tdata_reg[63:16]};
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output_axis_tkeep_reg <= {2'd0, save_eth_payload_tkeep_reg[7:2]};
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output_axis_tlast_reg <= save_eth_payload_tlast_reg;
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output_axis_tuser_reg <= save_eth_payload_tuser_reg;
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save_eth_payload_tkeep_reg <= 0;
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end
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if (write_hdr_out) begin
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output_axis_tdata_reg <= write_hdr_data;
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output_axis_tkeep_reg <= write_hdr_keep;
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output_axis_tlast_reg <= 0;
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output_axis_tuser_reg <= 0;
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end else if (write_hdr_temp) begin
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temp_axis_tdata_reg <= write_hdr_data;
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temp_axis_tkeep_reg <= write_hdr_keep;
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temp_axis_tlast_reg <= 0;
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temp_axis_tuser_reg <= 0;
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end else if (transfer_in_out) begin
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output_axis_tdata_reg <= {input_eth_payload_tdata[15:0], save_eth_payload_tdata_reg[63:16]};
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output_axis_tkeep_reg <= {input_eth_payload_tkeep[1:0], save_eth_payload_tkeep_reg[7:2]};
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output_axis_tlast_reg <= input_eth_payload_tlast & (input_eth_payload_tkeep[7:2] == 0);
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output_axis_tuser_reg <= input_eth_payload_tuser & (input_eth_payload_tkeep[7:2] == 0);
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end else if (transfer_in_temp) begin
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temp_axis_tdata_reg <= {input_eth_payload_tdata[15:0], save_eth_payload_tdata_reg[63:16]};
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temp_axis_tkeep_reg <= {input_eth_payload_tkeep[1:0], save_eth_payload_tkeep_reg[7:2]};
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temp_axis_tlast_reg <= input_eth_payload_tlast & (input_eth_payload_tkeep[7:2] == 0);
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temp_axis_tuser_reg <= input_eth_payload_tuser & (input_eth_payload_tkeep[7:2] == 0);
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end else if (transfer_temp_out) begin
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output_axis_tdata_reg <= temp_axis_tdata_reg;
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output_axis_tkeep_reg <= temp_axis_tkeep_reg;
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output_axis_tlast_reg <= temp_axis_tlast_reg;
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output_axis_tuser_reg <= temp_axis_tuser_reg;
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end
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end
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end
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endmodule
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