FPGA/verilog-ethernet
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Alex Forencich 70cc19ff15 Add MAC control layer to core 1G and 10G MAC modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-07-23 22:24:42 -07:00
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quartus
Reorganize timing constraints
2021-05-18 16:15:41 -07:00
quartus_pro
Add timing constraints for Quartus Prime Pro
2021-05-18 18:30:33 -07:00
vivado
Add MAC control layer to core 1G and 10G MAC modules
2023-07-23 22:24:42 -07:00