mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-14 06:43:18 +08:00
418 lines
13 KiB
Python
Executable File
418 lines
13 KiB
Python
Executable File
#!/usr/bin/env python
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"""axis_frame_join
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Generates an AXI Stream frame join module with a specific number of input ports
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Usage: axis_frame_join [OPTION]...
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-?, --help display this help and exit
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-p, --ports specify number of ports
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-n, --name specify module name
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-o, --output specify output file name
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"""
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import io
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import sys
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import getopt
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from math import *
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from jinja2 import Template
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class Usage(Exception):
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def __init__(self, msg):
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self.msg = msg
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def main(argv=None):
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if argv is None:
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argv = sys.argv
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try:
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try:
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opts, args = getopt.getopt(argv[1:], "?n:p:o:", ["help", "name=", "ports=", "output="])
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except getopt.error as msg:
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raise Usage(msg)
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# more code, unchanged
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except Usage as err:
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print(err.msg, file=sys.stderr)
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print("for help use --help", file=sys.stderr)
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return 2
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ports = 4
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name = None
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out_name = None
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# process options
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for o, a in opts:
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if o in ('-?', '--help'):
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print(__doc__)
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sys.exit(0)
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if o in ('-p', '--ports'):
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ports = int(a)
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if o in ('-n', '--name'):
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name = a
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if o in ('-o', '--outputs'):
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out_name = a
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if name is None:
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name = "axis_frame_join_{0}".format(ports)
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if out_name is None:
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out_name = name + ".v"
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print("Opening file '%s'..." % out_name)
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try:
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out_file = open(out_name, 'w')
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except Exception as ex:
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print("Error opening \"%s\": %s" %(out_name, ex.strerror), file=sys.stderr)
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exit(1)
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print("Generating {0} port AXI Stream frame joiner {1}...".format(ports, name))
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select_width = ceil(log2(ports))
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t = Template(u"""/*
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Copyright (c) 2014 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4-Stream {{n}} port frame joiner
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*/
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module {{name}} #
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(
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parameter ENABLE_TAG = 1
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI inputs
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*/
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{%- for p in ports %}
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input wire [7:0] input_{{p}}_axis_tdata,
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input wire input_{{p}}_axis_tvalid,
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output wire input_{{p}}_axis_tready,
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input wire input_{{p}}_axis_tlast,
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input wire input_{{p}}_axis_tuser,
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{% endfor %}
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/*
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* AXI output
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*/
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output wire [7:0] output_axis_tdata,
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output wire output_axis_tvalid,
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input wire output_axis_tready,
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output wire output_axis_tlast,
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output wire output_axis_tuser,
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/*
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* Configuration
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*/
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input wire [15:0] tag,
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/*
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* Status signals
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*/
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output wire busy
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);
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// state register
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localparam [1:0]
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STATE_IDLE = 2'd0,
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STATE_WRITE_TAG = 2'd1,
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STATE_TRANSFER = 2'd2;
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reg [1:0] state_reg = STATE_IDLE, state_next;
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reg [2:0] frame_ptr_reg = 0, frame_ptr_next;
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reg [{{w-1}}:0] port_sel_reg = 0, port_sel_next;
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reg busy_reg = 0, busy_next;
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reg [7:0] input_tdata;
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reg input_tvalid;
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reg input_tlast;
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reg input_tuser;
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reg output_tuser_reg = 0, output_tuser_next;
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{% for p in ports %}
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reg input_{{p}}_axis_tready_reg = 0, input_{{p}}_axis_tready_next;
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{%- endfor %}
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// internal datapath
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reg [7:0] output_axis_tdata_int;
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reg output_axis_tvalid_int;
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reg output_axis_tready_int = 0;
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reg output_axis_tlast_int;
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reg output_axis_tuser_int;
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wire output_axis_tready_int_early;
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{% for p in ports %}
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assign input_{{p}}_axis_tready = input_{{p}}_axis_tready_reg;
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{%- endfor %}
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assign busy = busy_reg;
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always @* begin
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// input port mux
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case (port_sel_reg)
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{%- for p in ports %}
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{{w}}'d{{p}}: begin
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input_tdata = input_{{p}}_axis_tdata;
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input_tvalid = input_{{p}}_axis_tvalid;
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input_tlast = input_{{p}}_axis_tlast;
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input_tuser = input_{{p}}_axis_tuser;
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end
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{%- endfor %}
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endcase
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end
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always @* begin
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state_next = 2'bz;
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frame_ptr_next = frame_ptr_reg;
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port_sel_next = port_sel_reg;
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{% for p in ports %}
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input_{{p}}_axis_tready_next = 0;
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{%- endfor %}
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output_axis_tdata_int = 0;
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output_axis_tvalid_int = 0;
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output_axis_tlast_int = 0;
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output_axis_tuser_int = 0;
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output_tuser_next = output_tuser_reg;
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case (state_reg)
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STATE_IDLE: begin
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// idle state - wait for data
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frame_ptr_next = 0;
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port_sel_next = 0;
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output_tuser_next = 0;
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if (ENABLE_TAG) begin
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// next cycle if started will send tag, so do not enable input
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input_0_axis_tready_next = 0;
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end else begin
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// next cycle if started will send data, so enable input
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input_0_axis_tready_next = output_axis_tready_int_early;
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end
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if (input_0_axis_tvalid) begin
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// input 0 valid; start transferring data
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if (ENABLE_TAG) begin
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// tag enabled, so transmit it
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if (output_axis_tready_int) begin
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// output is ready, so short-circuit first tag byte
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frame_ptr_next = 1;
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output_axis_tdata_int = tag[15:8];
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output_axis_tvalid_int = 1;
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end
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state_next = STATE_WRITE_TAG;
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end else begin
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// tag disabled, so transmit data
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if (output_axis_tready_int) begin
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// output is ready, so short-circuit first data byte
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output_axis_tdata_int = input_0_axis_tdata;
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output_axis_tvalid_int = 1;
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end
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state_next = STATE_TRANSFER;
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end
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end else begin
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state_next = STATE_IDLE;
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end
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end
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STATE_WRITE_TAG: begin
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// write tag data
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if (output_axis_tready_int) begin
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// output ready, so send tag byte
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state_next = STATE_WRITE_TAG;
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frame_ptr_next = frame_ptr_reg + 1;
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output_axis_tvalid_int = 1;
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case (frame_ptr_reg)
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2'd0: output_axis_tdata_int = tag[15:8];
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2'd1: begin
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// last tag byte - get ready to send data, enable input if ready
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output_axis_tdata_int = tag[7:0];
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input_0_axis_tready_next = output_axis_tready_int_early;
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state_next = STATE_TRANSFER;
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end
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endcase
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end else begin
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state_next = STATE_WRITE_TAG;
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end
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end
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STATE_TRANSFER: begin
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// transfer input data
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// set ready for current input
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case (port_sel_reg)
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{%- for p in ports %}
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{{w}}'d{{p}}: input_{{p}}_axis_tready_next = output_axis_tready_int_early;
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{%- endfor %}
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endcase
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if (input_tvalid & output_axis_tready_int) begin
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// output ready, transfer byte
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state_next = STATE_TRANSFER;
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output_axis_tdata_int = input_tdata;
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output_axis_tvalid_int = input_tvalid;
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if (input_tlast) begin
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// last flag received, switch to next port
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port_sel_next = port_sel_reg + 1;
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// save tuser - assert tuser out if ANY tuser asserts received
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output_tuser_next = output_tuser_next | input_tuser;
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// disable input
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{%- for p in ports %}
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input_{{p}}_axis_tready_next = 0;
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{%- endfor %}
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if (port_sel_reg == {{n-1}}) begin
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// last port - send tlast and tuser and revert to idle
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output_axis_tlast_int = 1;
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output_axis_tuser_int = output_tuser_next;
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state_next = STATE_IDLE;
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end else begin
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// otherwise, disable enable next port
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case (port_sel_next)
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{%- for p in ports %}
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{{w}}'d{{p}}: input_{{p}}_axis_tready_next = output_axis_tready_int_early;
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{%- endfor %}
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endcase
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end
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end
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end else begin
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state_next = STATE_TRANSFER;
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end
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end
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endcase
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end
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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state_reg <= STATE_IDLE;
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frame_ptr_reg <= 0;
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port_sel_reg <= 0;
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{%- for p in ports %}
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input_{{p}}_axis_tready_reg <= 0;
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{%- endfor %}
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output_tuser_reg <= 0;
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busy_reg <= 0;
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end else begin
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state_reg <= state_next;
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frame_ptr_reg <= frame_ptr_next;
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port_sel_reg <= port_sel_next;
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{% for p in ports %}
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input_{{p}}_axis_tready_reg <= input_{{p}}_axis_tready_next;
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{%- endfor %}
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output_tuser_reg <= output_tuser_next;
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busy_reg <= state_next != STATE_IDLE;
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end
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end
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// output datapath logic
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reg [7:0] output_axis_tdata_reg = 0;
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reg output_axis_tvalid_reg = 0;
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reg output_axis_tlast_reg = 0;
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reg output_axis_tuser_reg = 0;
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reg [7:0] temp_axis_tdata_reg = 0;
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reg temp_axis_tvalid_reg = 0;
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reg temp_axis_tlast_reg = 0;
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reg temp_axis_tuser_reg = 0;
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assign output_axis_tdata = output_axis_tdata_reg;
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assign output_axis_tvalid = output_axis_tvalid_reg;
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assign output_axis_tlast = output_axis_tlast_reg;
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assign output_axis_tuser = output_axis_tuser_reg;
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// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle
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assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & ~output_axis_tvalid_reg) | (~temp_axis_tvalid_reg & ~output_axis_tvalid_int);
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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output_axis_tdata_reg <= 0;
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output_axis_tvalid_reg <= 0;
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output_axis_tlast_reg <= 0;
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output_axis_tuser_reg <= 0;
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output_axis_tready_int <= 0;
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temp_axis_tdata_reg <= 0;
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temp_axis_tvalid_reg <= 0;
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temp_axis_tlast_reg <= 0;
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temp_axis_tuser_reg <= 0;
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end else begin
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// transfer sink ready state to source
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output_axis_tready_int <= output_axis_tready_int_early;
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if (output_axis_tready_int) begin
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// input is ready
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if (output_axis_tready | ~output_axis_tvalid_reg) begin
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// output is ready or currently not valid, transfer data to output
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output_axis_tdata_reg <= output_axis_tdata_int;
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output_axis_tvalid_reg <= output_axis_tvalid_int;
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output_axis_tlast_reg <= output_axis_tlast_int;
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output_axis_tuser_reg <= output_axis_tuser_int;
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end else begin
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// output is not ready, store input in temp
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temp_axis_tdata_reg <= output_axis_tdata_int;
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temp_axis_tvalid_reg <= output_axis_tvalid_int;
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temp_axis_tlast_reg <= output_axis_tlast_int;
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temp_axis_tuser_reg <= output_axis_tuser_int;
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end
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end else if (output_axis_tready) begin
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// input is not ready, but output is ready
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output_axis_tdata_reg <= temp_axis_tdata_reg;
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output_axis_tvalid_reg <= temp_axis_tvalid_reg;
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output_axis_tlast_reg <= temp_axis_tlast_reg;
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output_axis_tuser_reg <= temp_axis_tuser_reg;
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temp_axis_tdata_reg <= 0;
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temp_axis_tvalid_reg <= 0;
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temp_axis_tlast_reg <= 0;
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temp_axis_tuser_reg <= 0;
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end
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end
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end
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endmodule
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""")
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out_file.write(t.render(
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n=ports,
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w=select_width,
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name=name,
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ports=range(ports)
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))
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print("Done")
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if __name__ == "__main__":
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sys.exit(main())
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