FPGA/verilog-ethernet
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verilog-ethernet/example/AU250/fpga_25g/rtl
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Alex Forencich ea80d853ed Use unified 10G/25G design for Alveo U250 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-07-13 19:53:21 -07:00
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debounce_switch.v
Use unified 10G/25G design for Alveo U250
2023-07-13 19:53:21 -07:00
eth_xcvr_phy_wrapper.v
Use unified 10G/25G design for Alveo U250
2023-07-13 19:53:21 -07:00
fpga_core.v
Use unified 10G/25G design for Alveo U250
2023-07-13 19:53:21 -07:00
fpga.v
Use unified 10G/25G design for Alveo U250
2023-07-13 19:53:21 -07:00
sync_signal.v
Use unified 10G/25G design for Alveo U250
2023-07-13 19:53:21 -07:00