mirror of
https://github.com/alexforencich/verilog-ethernet.git
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135 lines
3.7 KiB
Verilog
135 lines
3.7 KiB
Verilog
/*
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Copyright (c) 2015-2016 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* Testbench for axis_frame_length_adjust
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*/
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module test_axis_frame_length_adjust_64;
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// Parameters
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localparam DATA_WIDTH = 64;
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localparam KEEP_WIDTH = (DATA_WIDTH/8);
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// Inputs
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reg clk = 0;
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reg rst = 0;
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reg [7:0] current_test = 0;
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reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
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reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0;
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reg input_axis_tvalid = 0;
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reg input_axis_tlast = 0;
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reg input_axis_tuser = 0;
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reg output_axis_tready = 0;
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reg status_ready = 0;
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reg [15:0] length_min = 0;
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reg [15:0] length_max = 0;
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// Outputs
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wire input_axis_tready;
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wire [DATA_WIDTH-1:0] output_axis_tdata;
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wire [KEEP_WIDTH-1:0] output_axis_tkeep;
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wire output_axis_tvalid;
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wire output_axis_tlast;
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wire output_axis_tuser;
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wire status_valid;
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wire status_frame_pad;
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wire status_frame_truncate;
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wire [15:0] status_frame_length;
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wire [15:0] status_frame_original_length;
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initial begin
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// myhdl integration
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$from_myhdl(
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clk,
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rst,
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current_test,
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input_axis_tdata,
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input_axis_tkeep,
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input_axis_tvalid,
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input_axis_tlast,
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input_axis_tuser,
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output_axis_tready,
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status_ready,
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length_min,
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length_max
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);
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$to_myhdl(
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input_axis_tready,
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output_axis_tdata,
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output_axis_tkeep,
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output_axis_tvalid,
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output_axis_tlast,
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output_axis_tuser,
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status_valid,
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status_frame_pad,
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status_frame_truncate,
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status_frame_length,
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status_frame_original_length
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);
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// dump file
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$dumpfile("test_axis_frame_length_adjust_64.lxt");
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$dumpvars(0, test_axis_frame_length_adjust_64);
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end
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axis_frame_length_adjust #(
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.DATA_WIDTH(DATA_WIDTH),
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.KEEP_WIDTH(KEEP_WIDTH)
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)
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UUT (
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.clk(clk),
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.rst(rst),
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// AXI input
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.input_axis_tdata(input_axis_tdata),
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.input_axis_tkeep(input_axis_tkeep),
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.input_axis_tvalid(input_axis_tvalid),
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.input_axis_tready(input_axis_tready),
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.input_axis_tlast(input_axis_tlast),
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.input_axis_tuser(input_axis_tuser),
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// AXI output
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.output_axis_tdata(output_axis_tdata),
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.output_axis_tkeep(output_axis_tkeep),
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.output_axis_tvalid(output_axis_tvalid),
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.output_axis_tready(output_axis_tready),
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.output_axis_tlast(output_axis_tlast),
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.output_axis_tuser(output_axis_tuser),
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// Status
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.status_valid(status_valid),
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.status_ready(status_ready),
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.status_frame_pad(status_frame_pad),
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.status_frame_truncate(status_frame_truncate),
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.status_frame_length(status_frame_length),
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.status_frame_original_length(status_frame_original_length),
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// Configuration
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.length_min(length_min),
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.length_max(length_max)
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);
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endmodule
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