mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-28 07:03:08 +08:00
193 lines
14 KiB
Verilog
193 lines
14 KiB
Verilog
// megafunction wizard: %10GBASE-R PHY v15.0%
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// GENERATION: XML
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// phy.v
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// Generated using ACDS version 15.0 153
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`timescale 1 ps / 1 ps
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module phy (
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input wire pll_ref_clk, // pll_ref_clk.clk
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output wire xgmii_rx_clk, // xgmii_rx_clk.clk
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output wire pll_locked, // pll_locked.export
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output wire tx_ready, // tx_ready.export
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input wire xgmii_tx_clk, // xgmii_tx_clk.clk
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output wire rx_ready, // rx_ready.export
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output wire [3:0] rx_data_ready, // rx_data_ready.export
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output wire [71:0] xgmii_rx_dc_0, // xgmii_rx_dc_0.data
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input wire rx_serial_data_0, // rx_serial_data_0.export
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output wire [71:0] xgmii_rx_dc_1, // xgmii_rx_dc_1.data
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input wire rx_serial_data_1, // rx_serial_data_1.export
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output wire [71:0] xgmii_rx_dc_2, // xgmii_rx_dc_2.data
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input wire rx_serial_data_2, // rx_serial_data_2.export
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output wire [71:0] xgmii_rx_dc_3, // xgmii_rx_dc_3.data
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input wire rx_serial_data_3, // rx_serial_data_3.export
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input wire [71:0] xgmii_tx_dc_0, // xgmii_tx_dc_0.data
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output wire [0:0] tx_serial_data_0, // tx_serial_data_0.export
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input wire [71:0] xgmii_tx_dc_1, // xgmii_tx_dc_1.data
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output wire [0:0] tx_serial_data_1, // tx_serial_data_1.export
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input wire [71:0] xgmii_tx_dc_2, // xgmii_tx_dc_2.data
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output wire [0:0] tx_serial_data_2, // tx_serial_data_2.export
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input wire [71:0] xgmii_tx_dc_3, // xgmii_tx_dc_3.data
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output wire [0:0] tx_serial_data_3, // tx_serial_data_3.export
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output wire [367:0] reconfig_from_xcvr, // reconfig_from_xcvr.reconfig_from_xcvr
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input wire [559:0] reconfig_to_xcvr, // reconfig_to_xcvr.reconfig_to_xcvr
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input wire phy_mgmt_clk, // phy_mgmt_clk.clk
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input wire phy_mgmt_clk_reset, // phy_mgmt_clk_reset.reset
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input wire [8:0] phy_mgmt_address, // phy_mgmt.address
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input wire phy_mgmt_read, // .read
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output wire [31:0] phy_mgmt_readdata, // .readdata
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input wire phy_mgmt_write, // .write
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input wire [31:0] phy_mgmt_writedata, // .writedata
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output wire phy_mgmt_waitrequest // .waitrequest
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);
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wire [3:0] phy_inst_tx_serial_data; // port fragment
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wire [287:0] phy_inst_xgmii_rx_dc; // port fragment
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altera_xcvr_10gbaser #(
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.device_family ("Stratix V"),
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.num_channels (4),
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.operation_mode ("duplex"),
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.external_pma_ctrl_config (0),
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.control_pin_out (0),
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.recovered_clk_out (0),
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.pll_locked_out (1),
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.ref_clk_freq ("644.53125 MHz"),
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.pma_mode (40),
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.pll_type ("CMU"),
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.starting_channel_number (0),
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.reconfig_interfaces (8),
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.rx_use_coreclk (0),
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.embedded_reset (1),
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.latadj (0),
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.high_precision_latadj (1),
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.tx_termination ("OCT_100_OHMS"),
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.tx_vod_selection (7),
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.tx_preemp_pretap (0),
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.tx_preemp_pretap_inv (0),
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.tx_preemp_tap_1 (15),
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.tx_preemp_tap_2 (0),
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.tx_preemp_tap_2_inv (0),
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.rx_common_mode ("0.82v"),
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.rx_termination ("OCT_100_OHMS"),
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.rx_eq_dc_gain (0),
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.rx_eq_ctrl (0),
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.mgmt_clk_in_mhz (150)
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) phy_inst (
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.pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk
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.xgmii_rx_clk (xgmii_rx_clk), // xgmii_rx_clk.clk
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.pll_locked (pll_locked), // pll_locked.export
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.tx_ready (tx_ready), // tx_ready.export
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.xgmii_tx_clk (xgmii_tx_clk), // xgmii_tx_clk.clk
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.rx_ready (rx_ready), // rx_ready.export
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.rx_data_ready (rx_data_ready), // rx_data_ready.export
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.xgmii_rx_dc (phy_inst_xgmii_rx_dc), // xgmii_rx_dc_0.data
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.rx_serial_data ({rx_serial_data_3,rx_serial_data_2,rx_serial_data_1,rx_serial_data_0}), // rx_serial_data_0.export
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.xgmii_tx_dc ({xgmii_tx_dc_3[71:0],xgmii_tx_dc_2[71:0],xgmii_tx_dc_1[71:0],xgmii_tx_dc_0[71:0]}), // xgmii_tx_dc_0.data
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.tx_serial_data (phy_inst_tx_serial_data), // tx_serial_data_0.export
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.reconfig_from_xcvr (reconfig_from_xcvr), // reconfig_from_xcvr.reconfig_from_xcvr
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.reconfig_to_xcvr (reconfig_to_xcvr), // reconfig_to_xcvr.reconfig_to_xcvr
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.phy_mgmt_clk (phy_mgmt_clk), // phy_mgmt_clk.clk
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.phy_mgmt_clk_reset (phy_mgmt_clk_reset), // phy_mgmt_clk_reset.reset
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.phy_mgmt_address (phy_mgmt_address), // phy_mgmt.address
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.phy_mgmt_read (phy_mgmt_read), // .read
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.phy_mgmt_readdata (phy_mgmt_readdata), // .readdata
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.phy_mgmt_write (phy_mgmt_write), // .write
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.phy_mgmt_writedata (phy_mgmt_writedata), // .writedata
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.phy_mgmt_waitrequest (phy_mgmt_waitrequest), // .waitrequest
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.rx_block_lock (), // (terminated)
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.rx_hi_ber (), // (terminated)
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.rx_recovered_clk (), // (terminated)
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.rx_coreclkin (1'b0), // (terminated)
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.gxb_pdn (1'b0), // (terminated)
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.pll_pdn (1'b0), // (terminated)
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.cal_blk_pdn (1'b0), // (terminated)
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.cal_blk_clk (1'b0), // (terminated)
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.tx_digitalreset (4'b0000), // (terminated)
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.tx_analogreset (4'b0000), // (terminated)
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.tx_cal_busy (), // (terminated)
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.pll_powerdown (4'b0000), // (terminated)
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.rx_digitalreset (4'b0000), // (terminated)
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.rx_analogreset (4'b0000), // (terminated)
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.rx_cal_busy (), // (terminated)
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.rx_is_lockedtodata (), // (terminated)
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.rx_latency_adj (), // (terminated)
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.tx_latency_adj () // (terminated)
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);
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assign tx_serial_data_0 = { phy_inst_tx_serial_data[0:0] };
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assign xgmii_rx_dc_0 = { phy_inst_xgmii_rx_dc[71:0] };
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assign tx_serial_data_1 = { phy_inst_tx_serial_data[1:1] };
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assign xgmii_rx_dc_1 = { phy_inst_xgmii_rx_dc[143:72] };
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assign xgmii_rx_dc_2 = { phy_inst_xgmii_rx_dc[215:144] };
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assign xgmii_rx_dc_3 = { phy_inst_xgmii_rx_dc[287:216] };
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assign tx_serial_data_2 = { phy_inst_tx_serial_data[2:2] };
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assign tx_serial_data_3 = { phy_inst_tx_serial_data[3:3] };
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endmodule
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// Retrieval info: <?xml version="1.0"?>
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//<!--
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// Generated by Altera MegaWizard Launcher Utility version 1.0
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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// ************************************************************
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// Copyright (C) 1991-2016 Altera Corporation
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// Any megafunction design, and related net list (encrypted or decrypted),
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// support information, device programming or simulation file, and any other
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// associated documentation or information provided by Altera or a partner
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// under Altera's Megafunction Partnership Program may be used only to
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// program PLD devices (but not masked PLD devices) from Altera. Any other
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// use of such megafunction design, net list, support information, device
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// programming or simulation file, or any other related documentation or
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// information is prohibited for any other purpose, including, but not
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// limited to modification, reverse engineering, de-compiling, or use with
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// any other silicon devices, unless such use is explicitly licensed under
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// a separate agreement with Altera or a megafunction partner. Title to
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// the intellectual property, including patents, copyrights, trademarks,
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// trade secrets, or maskworks, embodied in any such megafunction design,
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// net list, support information, device programming or simulation file, or
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// any other related documentation or information provided by Altera or a
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// megafunction partner, remains with Altera, the megafunction partner, or
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// their respective licensors. No other licenses, including any licenses
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// needed under any third party's intellectual property, are provided herein.
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//-->
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// Retrieval info: <instance entity-name="altera_xcvr_10gbaser" version="15.0" >
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// Retrieval info: <generic name="device_family" value="Stratix V" />
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// Retrieval info: <generic name="num_channels" value="4" />
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// Retrieval info: <generic name="operation_mode" value="duplex" />
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// Retrieval info: <generic name="external_pma_ctrl_config" value="0" />
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// Retrieval info: <generic name="control_pin_out" value="0" />
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// Retrieval info: <generic name="recovered_clk_out" value="0" />
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// Retrieval info: <generic name="pll_locked_out" value="1" />
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// Retrieval info: <generic name="gui_pll_type" value="CMU" />
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// Retrieval info: <generic name="ref_clk_freq" value="644.53125 MHz" />
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// Retrieval info: <generic name="pma_mode" value="40" />
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// Retrieval info: <generic name="starting_channel_number" value="0" />
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// Retrieval info: <generic name="sys_clk_in_hz" value="150000000" />
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// Retrieval info: <generic name="rx_use_coreclk" value="0" />
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// Retrieval info: <generic name="gui_embedded_reset" value="1" />
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// Retrieval info: <generic name="latadj" value="0" />
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// Retrieval info: <generic name="high_precision_latadj" value="1" />
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// Retrieval info: <generic name="tx_termination" value="OCT_100_OHMS" />
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// Retrieval info: <generic name="tx_vod_selection" value="7" />
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// Retrieval info: <generic name="tx_preemp_pretap" value="0" />
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// Retrieval info: <generic name="tx_preemp_pretap_inv" value="0" />
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// Retrieval info: <generic name="tx_preemp_tap_1" value="15" />
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// Retrieval info: <generic name="tx_preemp_tap_2" value="0" />
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// Retrieval info: <generic name="tx_preemp_tap_2_inv" value="0" />
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// Retrieval info: <generic name="rx_common_mode" value="0.82v" />
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// Retrieval info: <generic name="rx_termination" value="OCT_100_OHMS" />
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// Retrieval info: <generic name="rx_eq_dc_gain" value="0" />
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// Retrieval info: <generic name="rx_eq_ctrl" value="0" />
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// Retrieval info: <generic name="mgmt_clk_in_hz" value="150000000" />
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// Retrieval info: </instance>
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// IPFS_FILES : phy.vo
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// RELATED_FILES: phy.v, altera_xcvr_functions.sv, alt_reset_ctrl_lego.sv, alt_reset_ctrl_tgx_cdrauto.sv, alt_xcvr_resync.sv, alt_xcvr_csr_common_h.sv, alt_xcvr_csr_common.sv, alt_xcvr_csr_pcs8g_h.sv, alt_xcvr_csr_pcs8g.sv, alt_xcvr_csr_selector.sv, alt_xcvr_mgmt2dec.sv, altera_wait_generate.v, altera_10gbaser_phy_handshake_clock_crosser.v, altera_10gbaser_phy_clock_crosser.v, altera_10gbaser_phy_pipeline_stage.sv, altera_10gbaser_phy_pipeline_base.v, csr_pcs10gbaser_h.sv, csr_pcs10gbaser.sv, sv_pcs.sv, sv_pcs_ch.sv, sv_pma.sv, sv_reconfig_bundle_to_xcvr.sv, sv_reconfig_bundle_to_ip.sv, sv_reconfig_bundle_merger.sv, sv_rx_pma.sv, sv_tx_pma.sv, sv_tx_pma_ch.sv, sv_xcvr_h.sv, sv_xcvr_avmm_csr.sv, sv_xcvr_avmm_dcd.sv, sv_xcvr_avmm.sv, sv_xcvr_data_adapter.sv, sv_xcvr_native.sv, sv_xcvr_plls.sv, sv_hssi_10g_rx_pcs_rbc.sv, sv_hssi_10g_tx_pcs_rbc.sv, sv_hssi_8g_rx_pcs_rbc.sv, sv_hssi_8g_tx_pcs_rbc.sv, sv_hssi_8g_pcs_aggregate_rbc.sv, sv_hssi_common_pcs_pma_interface_rbc.sv, sv_hssi_common_pld_pcs_interface_rbc.sv, sv_hssi_pipe_gen1_2_rbc.sv, sv_hssi_pipe_gen3_rbc.sv, sv_hssi_rx_pcs_pma_interface_rbc.sv, sv_hssi_rx_pld_pcs_interface_rbc.sv, sv_hssi_tx_pcs_pma_interface_rbc.sv, sv_hssi_tx_pld_pcs_interface_rbc.sv, sv_xcvr_10gbaser_nr.sv, sv_xcvr_10gbaser_native.sv, altera_xcvr_10gbaser.sv, altera_xcvr_reset_control.sv, alt_xcvr_reset_counter.sv, alt_xcvr_arbiter.sv, alt_xcvr_m2s.sv
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