FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-14 06:43:18 +08:00
Code Issues Projects Releases Wiki Activity
verilog-ethernet/example/AU200/fpga_25g/fpga
History
Alex Forencich 0b18633bb1 Use unified 10G/25G design for Alveo U200 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-07-13 19:49:25 -07:00
..
config.tcl
Use unified 10G/25G design for Alveo U200
2023-07-13 19:49:25 -07:00
Makefile
Use unified 10G/25G design for Alveo U200
2023-07-13 19:49:25 -07:00