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verilog-ethernet/example/AU50/fpga_25g/ip
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Alex Forencich a221adc468 Use unified 10G/25G design for Alveo U50 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-07-13 20:40:38 -07:00
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eth_xcvr_gt.tcl
Use unified 10G/25G design for Alveo U50
2023-07-13 20:40:38 -07:00