mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-28 07:03:08 +08:00
475 lines
12 KiB
Verilog
475 lines
12 KiB
Verilog
/*
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Copyright (c) 2014-2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* FPGA top-level module
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*/
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module fpga (
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/*
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* GPIO
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*/
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output wire qsfp_led_act,
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output wire qsfp_led_stat_g,
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output wire qsfp_led_stat_y,
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output wire hbm_cattrip,
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/*
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* Ethernet: QSFP28
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*/
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output wire qsfp_tx1_p,
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output wire qsfp_tx1_n,
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input wire qsfp_rx1_p,
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input wire qsfp_rx1_n,
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output wire qsfp_tx2_p,
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output wire qsfp_tx2_n,
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input wire qsfp_rx2_p,
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input wire qsfp_rx2_n,
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output wire qsfp_tx3_p,
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output wire qsfp_tx3_n,
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input wire qsfp_rx3_p,
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input wire qsfp_rx3_n,
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output wire qsfp_tx4_p,
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output wire qsfp_tx4_n,
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input wire qsfp_rx4_p,
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input wire qsfp_rx4_n,
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input wire qsfp_mgt_refclk_0_p,
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input wire qsfp_mgt_refclk_0_n
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// input wire qsfp_mgt_refclk_1_p,
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// input wire qsfp_mgt_refclk_1_n
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);
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// Clock and reset
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wire clk_161mhz_ref_int;
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// Internal 125 MHz clock
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wire clk_125mhz_mmcm_out;
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wire clk_125mhz_int;
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wire rst_125mhz_int;
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// Internal 156.25 MHz clock
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wire clk_156mhz_int;
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wire rst_156mhz_int;
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wire mmcm_rst = 1'b0;
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wire mmcm_locked;
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wire mmcm_clkfb;
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// MMCM instance
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// 161.13 MHz in, 125 MHz out
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// PFD range: 10 MHz to 500 MHz
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// VCO range: 800 MHz to 1600 MHz
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// M = 64, D = 11 sets Fvco = 937.5 MHz (in range)
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// Divide by 7.5 to get output frequency of 125 MHz
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MMCME4_BASE #(
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.BANDWIDTH("OPTIMIZED"),
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.CLKOUT0_DIVIDE_F(7.5),
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT0_PHASE(0),
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.CLKOUT1_DIVIDE(1),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT1_PHASE(0),
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.CLKOUT2_DIVIDE(1),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT2_PHASE(0),
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.CLKOUT3_DIVIDE(1),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT3_PHASE(0),
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.CLKOUT4_DIVIDE(1),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT4_PHASE(0),
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.CLKOUT5_DIVIDE(1),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT5_PHASE(0),
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.CLKOUT6_DIVIDE(1),
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.CLKOUT6_DUTY_CYCLE(0.5),
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.CLKOUT6_PHASE(0),
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.CLKFBOUT_MULT_F(64),
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.CLKFBOUT_PHASE(0),
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.DIVCLK_DIVIDE(11),
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.REF_JITTER1(0.010),
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.CLKIN1_PERIOD(6.206),
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.STARTUP_WAIT("FALSE"),
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.CLKOUT4_CASCADE("FALSE")
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)
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clk_mmcm_inst (
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.CLKIN1(clk_161mhz_ref_int),
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.CLKFBIN(mmcm_clkfb),
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.RST(mmcm_rst),
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.PWRDWN(1'b0),
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.CLKOUT0(clk_125mhz_mmcm_out),
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.CLKOUT0B(),
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.CLKOUT1(),
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.CLKOUT1B(),
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.CLKOUT2(),
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.CLKOUT2B(),
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.CLKOUT3(),
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.CLKOUT3B(),
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.CLKOUT4(),
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.CLKOUT5(),
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.CLKOUT6(),
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.CLKFBOUT(mmcm_clkfb),
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.CLKFBOUTB(),
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.LOCKED(mmcm_locked)
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);
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BUFG
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clk_125mhz_bufg_inst (
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.I(clk_125mhz_mmcm_out),
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.O(clk_125mhz_int)
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);
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sync_reset #(
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.N(4)
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)
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sync_reset_125mhz_inst (
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.clk(clk_125mhz_int),
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.rst(~mmcm_locked),
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.out(rst_125mhz_int)
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);
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// GPIO
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assign hbm_cattrip = 1'b0;
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// XGMII 10G PHY
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wire qsfp_tx_clk_1_int;
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wire qsfp_tx_rst_1_int;
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wire [63:0] qsfp_txd_1_int;
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wire [7:0] qsfp_txc_1_int;
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wire qsfp_rx_clk_1_int;
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wire qsfp_rx_rst_1_int;
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wire [63:0] qsfp_rxd_1_int;
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wire [7:0] qsfp_rxc_1_int;
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wire qsfp_tx_clk_2_int;
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wire qsfp_tx_rst_2_int;
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wire [63:0] qsfp_txd_2_int;
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wire [7:0] qsfp_txc_2_int;
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wire qsfp_rx_clk_2_int;
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wire qsfp_rx_rst_2_int;
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wire [63:0] qsfp_rxd_2_int;
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wire [7:0] qsfp_rxc_2_int;
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wire qsfp_tx_clk_3_int;
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wire qsfp_tx_rst_3_int;
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wire [63:0] qsfp_txd_3_int;
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wire [7:0] qsfp_txc_3_int;
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wire qsfp_rx_clk_3_int;
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wire qsfp_rx_rst_3_int;
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wire [63:0] qsfp_rxd_3_int;
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wire [7:0] qsfp_rxc_3_int;
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wire qsfp_tx_clk_4_int;
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wire qsfp_tx_rst_4_int;
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wire [63:0] qsfp_txd_4_int;
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wire [7:0] qsfp_txc_4_int;
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wire qsfp_rx_clk_4_int;
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wire qsfp_rx_rst_4_int;
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wire [63:0] qsfp_rxd_4_int;
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wire [7:0] qsfp_rxc_4_int;
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assign clk_156mhz_int = qsfp_tx_clk_1_int;
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assign rst_156mhz_int = qsfp_tx_rst_1_int;
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wire qsfp_rx_block_lock_1;
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wire qsfp_rx_block_lock_2;
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wire qsfp_rx_block_lock_3;
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wire qsfp_rx_block_lock_4;
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wire qsfp_gtpowergood;
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wire qsfp_mgt_refclk_0;
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wire qsfp_mgt_refclk_0_int;
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wire qsfp_mgt_refclk_0_bufg;
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assign clk_161mhz_ref_int = qsfp_mgt_refclk_0_bufg;
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IBUFDS_GTE4 ibufds_gte4_qsfp_mgt_refclk_0_inst (
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.I (qsfp_mgt_refclk_0_p),
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.IB (qsfp_mgt_refclk_0_n),
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.CEB (1'b0),
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.O (qsfp_mgt_refclk_0),
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.ODIV2 (qsfp_mgt_refclk_0_int)
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);
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BUFG_GT bufg_gt_refclk_inst (
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.CE (qsfp_gtpowergood),
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.CEMASK (1'b1),
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.CLR (1'b0),
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.CLRMASK (1'b1),
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.DIV (3'd0),
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.I (qsfp_mgt_refclk_0_int),
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.O (qsfp_mgt_refclk_0_bufg)
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);
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wire qsfp_qpll0lock;
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wire qsfp_qpll0outclk;
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wire qsfp_qpll0outrefclk;
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eth_xcvr_phy_wrapper #(
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.HAS_COMMON(1)
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)
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qsfp_phy_1_inst (
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.xcvr_ctrl_clk(clk_125mhz_int),
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.xcvr_ctrl_rst(rst_125mhz_int),
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// Common
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.xcvr_gtpowergood_out(qsfp_gtpowergood),
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// PLL out
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.xcvr_gtrefclk00_in(qsfp_mgt_refclk_0),
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.xcvr_qpll0lock_out(qsfp_qpll0lock),
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.xcvr_qpll0outclk_out(qsfp_qpll0outclk),
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.xcvr_qpll0outrefclk_out(qsfp_qpll0outrefclk),
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// PLL in
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.xcvr_qpll0lock_in(1'b0),
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.xcvr_qpll0reset_out(),
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.xcvr_qpll0clk_in(1'b0),
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.xcvr_qpll0refclk_in(1'b0),
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// Serial data
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.xcvr_txp(qsfp_tx1_p),
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.xcvr_txn(qsfp_tx1_n),
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.xcvr_rxp(qsfp_rx1_p),
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.xcvr_rxn(qsfp_rx1_n),
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// PHY connections
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.phy_tx_clk(qsfp_tx_clk_1_int),
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.phy_tx_rst(qsfp_tx_rst_1_int),
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.phy_xgmii_txd(qsfp_txd_1_int),
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.phy_xgmii_txc(qsfp_txc_1_int),
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.phy_rx_clk(qsfp_rx_clk_1_int),
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.phy_rx_rst(qsfp_rx_rst_1_int),
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.phy_xgmii_rxd(qsfp_rxd_1_int),
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.phy_xgmii_rxc(qsfp_rxc_1_int),
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.phy_tx_bad_block(),
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.phy_rx_error_count(),
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.phy_rx_bad_block(),
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.phy_rx_sequence_error(),
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.phy_rx_block_lock(qsfp_rx_block_lock_1),
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.phy_rx_high_ber(),
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.phy_tx_prbs31_enable(),
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.phy_rx_prbs31_enable()
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);
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eth_xcvr_phy_wrapper #(
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.HAS_COMMON(0)
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)
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qsfp_phy_2_inst (
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.xcvr_ctrl_clk(clk_125mhz_int),
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.xcvr_ctrl_rst(rst_125mhz_int),
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// Common
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.xcvr_gtpowergood_out(),
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// PLL out
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.xcvr_gtrefclk00_in(1'b0),
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.xcvr_qpll0lock_out(),
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.xcvr_qpll0outclk_out(),
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.xcvr_qpll0outrefclk_out(),
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// PLL in
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.xcvr_qpll0lock_in(qsfp_qpll0lock),
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.xcvr_qpll0reset_out(),
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.xcvr_qpll0clk_in(qsfp_qpll0outclk),
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.xcvr_qpll0refclk_in(qsfp_qpll0outrefclk),
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// Serial data
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.xcvr_txp(qsfp_tx2_p),
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.xcvr_txn(qsfp_tx2_n),
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.xcvr_rxp(qsfp_rx2_p),
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.xcvr_rxn(qsfp_rx2_n),
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// PHY connections
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.phy_tx_clk(qsfp_tx_clk_2_int),
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.phy_tx_rst(qsfp_tx_rst_2_int),
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.phy_xgmii_txd(qsfp_txd_2_int),
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.phy_xgmii_txc(qsfp_txc_2_int),
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.phy_rx_clk(qsfp_rx_clk_2_int),
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.phy_rx_rst(qsfp_rx_rst_2_int),
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.phy_xgmii_rxd(qsfp_rxd_2_int),
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.phy_xgmii_rxc(qsfp_rxc_2_int),
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.phy_tx_bad_block(),
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.phy_rx_error_count(),
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.phy_rx_bad_block(),
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.phy_rx_sequence_error(),
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.phy_rx_block_lock(qsfp_rx_block_lock_2),
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.phy_rx_high_ber(),
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.phy_tx_prbs31_enable(),
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.phy_rx_prbs31_enable()
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);
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eth_xcvr_phy_wrapper #(
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.HAS_COMMON(0)
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)
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qsfp_phy_3_inst (
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.xcvr_ctrl_clk(clk_125mhz_int),
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.xcvr_ctrl_rst(rst_125mhz_int),
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// Common
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.xcvr_gtpowergood_out(),
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// PLL out
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.xcvr_gtrefclk00_in(1'b0),
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.xcvr_qpll0lock_out(),
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.xcvr_qpll0outclk_out(),
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.xcvr_qpll0outrefclk_out(),
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// PLL in
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.xcvr_qpll0lock_in(qsfp_qpll0lock),
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.xcvr_qpll0reset_out(),
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.xcvr_qpll0clk_in(qsfp_qpll0outclk),
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.xcvr_qpll0refclk_in(qsfp_qpll0outrefclk),
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// Serial data
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.xcvr_txp(qsfp_tx3_p),
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.xcvr_txn(qsfp_tx3_n),
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.xcvr_rxp(qsfp_rx3_p),
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.xcvr_rxn(qsfp_rx3_n),
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// PHY connections
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.phy_tx_clk(qsfp_tx_clk_3_int),
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.phy_tx_rst(qsfp_tx_rst_3_int),
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.phy_xgmii_txd(qsfp_txd_3_int),
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.phy_xgmii_txc(qsfp_txc_3_int),
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.phy_rx_clk(qsfp_rx_clk_3_int),
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.phy_rx_rst(qsfp_rx_rst_3_int),
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.phy_xgmii_rxd(qsfp_rxd_3_int),
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.phy_xgmii_rxc(qsfp_rxc_3_int),
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.phy_tx_bad_block(),
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.phy_rx_error_count(),
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.phy_rx_bad_block(),
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.phy_rx_sequence_error(),
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.phy_rx_block_lock(qsfp_rx_block_lock_3),
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.phy_rx_high_ber(),
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.phy_tx_prbs31_enable(),
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.phy_rx_prbs31_enable()
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);
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eth_xcvr_phy_wrapper #(
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.HAS_COMMON(0)
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)
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qsfp_phy_4_inst (
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.xcvr_ctrl_clk(clk_125mhz_int),
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.xcvr_ctrl_rst(rst_125mhz_int),
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// Common
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.xcvr_gtpowergood_out(),
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// PLL out
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.xcvr_gtrefclk00_in(1'b0),
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.xcvr_qpll0lock_out(),
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.xcvr_qpll0outclk_out(),
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.xcvr_qpll0outrefclk_out(),
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// PLL in
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.xcvr_qpll0lock_in(qsfp_qpll0lock),
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.xcvr_qpll0reset_out(),
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.xcvr_qpll0clk_in(qsfp_qpll0outclk),
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.xcvr_qpll0refclk_in(qsfp_qpll0outrefclk),
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// Serial data
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.xcvr_txp(qsfp_tx4_p),
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.xcvr_txn(qsfp_tx4_n),
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.xcvr_rxp(qsfp_rx4_p),
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.xcvr_rxn(qsfp_rx4_n),
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// PHY connections
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.phy_tx_clk(qsfp_tx_clk_4_int),
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.phy_tx_rst(qsfp_tx_rst_4_int),
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.phy_xgmii_txd(qsfp_txd_4_int),
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.phy_xgmii_txc(qsfp_txc_4_int),
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.phy_rx_clk(qsfp_rx_clk_4_int),
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.phy_rx_rst(qsfp_rx_rst_4_int),
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.phy_xgmii_rxd(qsfp_rxd_4_int),
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.phy_xgmii_rxc(qsfp_rxc_4_int),
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.phy_tx_bad_block(),
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.phy_rx_error_count(),
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.phy_rx_bad_block(),
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.phy_rx_sequence_error(),
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.phy_rx_block_lock(qsfp_rx_block_lock_4),
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.phy_rx_high_ber(),
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.phy_tx_prbs31_enable(),
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.phy_rx_prbs31_enable()
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);
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fpga_core
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core_inst (
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/*
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* Clock: 156.25 MHz
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* Synchronous reset
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*/
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.clk(clk_156mhz_int),
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.rst(rst_156mhz_int),
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/*
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* GPIO
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*/
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.qsfp_led_act(qsfp_led_act),
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.qsfp_led_stat_g(qsfp_led_stat_g),
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.qsfp_led_stat_y(qsfp_led_stat_y),
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/*
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* Ethernet: QSFP28
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*/
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.qsfp_tx_clk_1(qsfp_tx_clk_1_int),
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.qsfp_tx_rst_1(qsfp_tx_rst_1_int),
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.qsfp_txd_1(qsfp_txd_1_int),
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.qsfp_txc_1(qsfp_txc_1_int),
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.qsfp_rx_clk_1(qsfp_rx_clk_1_int),
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.qsfp_rx_rst_1(qsfp_rx_rst_1_int),
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.qsfp_rxd_1(qsfp_rxd_1_int),
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.qsfp_rxc_1(qsfp_rxc_1_int),
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.qsfp_tx_clk_2(qsfp_tx_clk_2_int),
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.qsfp_tx_rst_2(qsfp_tx_rst_2_int),
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.qsfp_txd_2(qsfp_txd_2_int),
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.qsfp_txc_2(qsfp_txc_2_int),
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.qsfp_rx_clk_2(qsfp_rx_clk_2_int),
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.qsfp_rx_rst_2(qsfp_rx_rst_2_int),
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.qsfp_rxd_2(qsfp_rxd_2_int),
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.qsfp_rxc_2(qsfp_rxc_2_int),
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.qsfp_tx_clk_3(qsfp_tx_clk_3_int),
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.qsfp_tx_rst_3(qsfp_tx_rst_3_int),
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.qsfp_txd_3(qsfp_txd_3_int),
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.qsfp_txc_3(qsfp_txc_3_int),
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.qsfp_rx_clk_3(qsfp_rx_clk_3_int),
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.qsfp_rx_rst_3(qsfp_rx_rst_3_int),
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.qsfp_rxd_3(qsfp_rxd_3_int),
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.qsfp_rxc_3(qsfp_rxc_3_int),
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|
.qsfp_tx_clk_4(qsfp_tx_clk_4_int),
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.qsfp_tx_rst_4(qsfp_tx_rst_4_int),
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|
.qsfp_txd_4(qsfp_txd_4_int),
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|
.qsfp_txc_4(qsfp_txc_4_int),
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|
.qsfp_rx_clk_4(qsfp_rx_clk_4_int),
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|
.qsfp_rx_rst_4(qsfp_rx_rst_4_int),
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|
.qsfp_rxd_4(qsfp_rxd_4_int),
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.qsfp_rxc_4(qsfp_rxc_4_int)
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|
);
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endmodule
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`resetall
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