mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-14 06:43:18 +08:00
257 lines
7.7 KiB
Verilog
257 lines
7.7 KiB
Verilog
/*
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Copyright (c) 2019 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* Testbench for eth_mac_10g_fifo
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*/
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module test_eth_mac_10g_fifo_ptp_32;
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// Parameters
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parameter DATA_WIDTH = 32;
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parameter CTRL_WIDTH = (DATA_WIDTH/8);
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parameter AXIS_DATA_WIDTH = DATA_WIDTH;
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parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8);
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parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8);
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parameter ENABLE_PADDING = 1;
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parameter ENABLE_DIC = 1;
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parameter MIN_FRAME_LENGTH = 64;
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parameter TX_FIFO_DEPTH = 4096;
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parameter TX_FIFO_PIPELINE_OUTPUT = 2;
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parameter TX_FRAME_FIFO = 1;
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parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO;
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parameter TX_DROP_WHEN_FULL = 0;
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parameter RX_FIFO_DEPTH = 4096;
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parameter RX_FIFO_PIPELINE_OUTPUT = 2;
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parameter RX_FRAME_FIFO = 1;
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parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO;
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parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO;
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parameter LOGIC_PTP_PERIOD_NS = 4'h3;
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parameter LOGIC_PTP_PERIOD_FNS = 16'h3333;
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parameter PTP_PERIOD_NS = 4'h3;
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parameter PTP_PERIOD_FNS = 16'h3333;
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parameter PTP_USE_SAMPLE_CLOCK = 0;
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parameter TX_PTP_TS_ENABLE = 1;
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parameter RX_PTP_TS_ENABLE = 1;
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parameter TX_PTP_TS_FIFO_DEPTH = 64;
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parameter RX_PTP_TS_FIFO_DEPTH = 64;
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parameter PTP_TS_WIDTH = 96;
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parameter TX_PTP_TAG_ENABLE = 1;
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parameter PTP_TAG_WIDTH = 16;
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// Inputs
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reg clk = 0;
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reg rst = 0;
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reg [7:0] current_test = 0;
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reg rx_clk = 0;
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reg rx_rst = 0;
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reg tx_clk = 0;
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reg tx_rst = 0;
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reg logic_clk = 0;
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reg logic_rst = 0;
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reg ptp_sample_clk = 0;
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reg [AXIS_DATA_WIDTH-1:0] tx_axis_tdata = 0;
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reg [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep = 0;
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reg tx_axis_tvalid = 0;
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reg tx_axis_tlast = 0;
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reg tx_axis_tuser = 0;
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reg [PTP_TAG_WIDTH-1:0] s_axis_tx_ptp_ts_tag = 0;
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reg s_axis_tx_ptp_ts_valid = 0;
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reg m_axis_tx_ptp_ts_ready = 0;
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reg rx_axis_tready = 0;
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reg m_axis_rx_ptp_ts_ready = 0;
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reg [DATA_WIDTH-1:0] xgmii_rxd = 0;
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reg [CTRL_WIDTH-1:0] xgmii_rxc = 0;
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reg [PTP_TS_WIDTH-1:0] ptp_ts_96 = 0;
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reg [7:0] ifg_delay = 0;
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// Outputs
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wire tx_axis_tready;
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wire s_axis_tx_ptp_ts_ready;
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wire [PTP_TS_WIDTH-1:0] m_axis_tx_ptp_ts_96;
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wire [PTP_TAG_WIDTH-1:0] m_axis_tx_ptp_ts_tag;
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wire m_axis_tx_ptp_ts_valid;
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wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata;
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wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep;
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wire rx_axis_tvalid;
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wire rx_axis_tlast;
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wire rx_axis_tuser;
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wire [PTP_TS_WIDTH-1:0] m_axis_rx_ptp_ts_96;
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wire m_axis_rx_ptp_ts_valid;
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wire [DATA_WIDTH-1:0] xgmii_txd;
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wire [CTRL_WIDTH-1:0] xgmii_txc;
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wire tx_error_underflow;
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wire tx_fifo_overflow;
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wire tx_fifo_bad_frame;
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wire tx_fifo_good_frame;
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wire rx_error_bad_frame;
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wire rx_error_bad_fcs;
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wire rx_fifo_overflow;
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wire rx_fifo_bad_frame;
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wire rx_fifo_good_frame;
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initial begin
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// myhdl integration
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$from_myhdl(
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clk,
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rst,
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current_test,
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rx_clk,
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rx_rst,
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tx_clk,
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tx_rst,
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logic_clk,
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logic_rst,
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ptp_sample_clk,
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tx_axis_tdata,
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tx_axis_tkeep,
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tx_axis_tvalid,
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tx_axis_tlast,
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tx_axis_tuser,
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s_axis_tx_ptp_ts_tag,
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s_axis_tx_ptp_ts_valid,
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m_axis_tx_ptp_ts_ready,
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rx_axis_tready,
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m_axis_rx_ptp_ts_ready,
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xgmii_rxd,
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xgmii_rxc,
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ptp_ts_96,
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ifg_delay
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);
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$to_myhdl(
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tx_axis_tready,
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s_axis_tx_ptp_ts_ready,
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m_axis_tx_ptp_ts_96,
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m_axis_tx_ptp_ts_tag,
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m_axis_tx_ptp_ts_valid,
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rx_axis_tdata,
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rx_axis_tkeep,
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rx_axis_tvalid,
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rx_axis_tlast,
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rx_axis_tuser,
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m_axis_rx_ptp_ts_96,
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m_axis_rx_ptp_ts_valid,
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xgmii_txd,
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xgmii_txc,
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tx_error_underflow,
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tx_fifo_overflow,
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tx_fifo_bad_frame,
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tx_fifo_good_frame,
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rx_error_bad_frame,
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rx_error_bad_fcs,
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rx_fifo_overflow,
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rx_fifo_bad_frame,
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rx_fifo_good_frame
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);
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// dump file
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$dumpfile("test_eth_mac_10g_fifo_ptp_32.lxt");
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$dumpvars(0, test_eth_mac_10g_fifo_ptp_32);
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end
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eth_mac_10g_fifo #(
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.DATA_WIDTH(DATA_WIDTH),
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.CTRL_WIDTH(CTRL_WIDTH),
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.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
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.AXIS_KEEP_ENABLE(AXIS_KEEP_ENABLE),
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.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
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.ENABLE_PADDING(ENABLE_PADDING),
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.ENABLE_DIC(ENABLE_DIC),
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.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
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.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
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.TX_FIFO_PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT),
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.TX_FRAME_FIFO(TX_FRAME_FIFO),
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.TX_DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
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.TX_DROP_WHEN_FULL(TX_DROP_WHEN_FULL),
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.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
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.RX_FIFO_PIPELINE_OUTPUT(RX_FIFO_PIPELINE_OUTPUT),
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.RX_FRAME_FIFO(RX_FRAME_FIFO),
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.RX_DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
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.RX_DROP_WHEN_FULL(RX_DROP_WHEN_FULL),
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.LOGIC_PTP_PERIOD_NS(LOGIC_PTP_PERIOD_NS),
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.LOGIC_PTP_PERIOD_FNS(LOGIC_PTP_PERIOD_FNS),
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.PTP_PERIOD_NS(PTP_PERIOD_NS),
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.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
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.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
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.TX_PTP_TS_ENABLE(TX_PTP_TS_ENABLE),
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.RX_PTP_TS_ENABLE(RX_PTP_TS_ENABLE),
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.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
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.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
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.PTP_TS_WIDTH(PTP_TS_WIDTH),
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.TX_PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE),
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.PTP_TAG_WIDTH(PTP_TAG_WIDTH)
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)
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UUT (
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.rx_clk(rx_clk),
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.rx_rst(rx_rst),
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.tx_clk(tx_clk),
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.tx_rst(tx_rst),
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.logic_clk(logic_clk),
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.logic_rst(logic_rst),
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.ptp_sample_clk(ptp_sample_clk),
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.tx_axis_tdata(tx_axis_tdata),
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.tx_axis_tkeep(tx_axis_tkeep),
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.tx_axis_tvalid(tx_axis_tvalid),
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.tx_axis_tready(tx_axis_tready),
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.tx_axis_tlast(tx_axis_tlast),
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.tx_axis_tuser(tx_axis_tuser),
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.s_axis_tx_ptp_ts_tag(s_axis_tx_ptp_ts_tag),
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.s_axis_tx_ptp_ts_valid(s_axis_tx_ptp_ts_valid),
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.s_axis_tx_ptp_ts_ready(s_axis_tx_ptp_ts_ready),
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.m_axis_tx_ptp_ts_96(m_axis_tx_ptp_ts_96),
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.m_axis_tx_ptp_ts_tag(m_axis_tx_ptp_ts_tag),
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.m_axis_tx_ptp_ts_valid(m_axis_tx_ptp_ts_valid),
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.m_axis_tx_ptp_ts_ready(m_axis_tx_ptp_ts_ready),
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.rx_axis_tdata(rx_axis_tdata),
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.rx_axis_tkeep(rx_axis_tkeep),
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.rx_axis_tvalid(rx_axis_tvalid),
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.rx_axis_tready(rx_axis_tready),
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.rx_axis_tlast(rx_axis_tlast),
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.rx_axis_tuser(rx_axis_tuser),
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.m_axis_rx_ptp_ts_96(m_axis_rx_ptp_ts_96),
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.m_axis_rx_ptp_ts_valid(m_axis_rx_ptp_ts_valid),
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.m_axis_rx_ptp_ts_ready(m_axis_rx_ptp_ts_ready),
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.xgmii_rxd(xgmii_rxd),
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.xgmii_rxc(xgmii_rxc),
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.xgmii_txd(xgmii_txd),
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.xgmii_txc(xgmii_txc),
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.tx_error_underflow(tx_error_underflow),
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.tx_fifo_overflow(tx_fifo_overflow),
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.tx_fifo_bad_frame(tx_fifo_bad_frame),
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.tx_fifo_good_frame(tx_fifo_good_frame),
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.rx_error_bad_frame(rx_error_bad_frame),
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.rx_error_bad_fcs(rx_error_bad_fcs),
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.rx_fifo_overflow(rx_fifo_overflow),
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.rx_fifo_bad_frame(rx_fifo_bad_frame),
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.rx_fifo_good_frame(rx_fifo_good_frame),
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.ptp_ts_96(ptp_ts_96),
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.ifg_delay(ifg_delay)
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);
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endmodule
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