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FPGA
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verilog-ethernet
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verilog-ethernet
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example
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DE5-Net
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fpga
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History
Alex Forencich
c2e459c971
Connect transceiver control lines
2017-03-09 17:14:14 -08:00
..
debounce_switch.v
Add 10G reference design for DE5-Net
2016-01-25 00:53:06 -08:00
fpga_core.v
Update UDP modules and example designs to utilize UDP checksum modules
2016-09-30 22:15:21 -07:00
fpga.v
Connect transceiver control lines
2017-03-09 17:14:14 -08:00
i2c_master.v
Add 10G reference design for DE5-Net
2016-01-25 00:53:06 -08:00
si570_i2c_init.v
Add 10G reference design for DE5-Net
2016-01-25 00:53:06 -08:00
sync_reset.v
Add 10G reference design for DE5-Net
2016-01-25 00:53:06 -08:00
sync_signal.v
Add 10G reference design for DE5-Net
2016-01-25 00:53:06 -08:00
