mirror of
https://github.com/alexforencich/verilog-ethernet.git
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134 lines
3.9 KiB
Verilog
134 lines
3.9 KiB
Verilog
/*
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Copyright (c) 2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* 10G Ethernet PHY frame sync
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*/
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module eth_phy_10g_rx_frame_sync #
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(
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parameter HDR_WIDTH = 2,
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parameter SLIP_COUNT_WIDTH = 3
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)
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(
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input wire clk,
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input wire rst,
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/*
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* SERDES interface
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*/
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input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
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output wire serdes_rx_bitslip,
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/*
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* Status
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*/
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output wire rx_block_lock
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);
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// bus width assertions
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initial begin
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if (HDR_WIDTH != 2) begin
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$error("Error: HDR_WIDTH must be 2");
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$finish;
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end
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end
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localparam [1:0]
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SYNC_DATA = 2'b10,
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SYNC_CTRL = 2'b01;
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reg [5:0] sh_count_reg = 6'd0, sh_count_next;
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reg [3:0] sh_invalid_count_reg = 4'd0, sh_invalid_count_next;
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reg [SLIP_COUNT_WIDTH-1:0] slip_count_reg = 0, slip_count_next;
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reg serdes_rx_bitslip_reg = 1'b0, serdes_rx_bitslip_next;
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reg rx_block_lock_reg = 1'b0, rx_block_lock_next;
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assign serdes_rx_bitslip = serdes_rx_bitslip_reg;
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assign rx_block_lock = rx_block_lock_reg;
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always @* begin
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sh_count_next = sh_count_reg;
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sh_invalid_count_next = sh_invalid_count_reg;
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slip_count_next = slip_count_reg;
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serdes_rx_bitslip_next = 1'b0;
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rx_block_lock_next = rx_block_lock_reg;
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if (slip_count_reg) begin
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slip_count_next = slip_count_reg-1;
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end else if (serdes_rx_hdr == SYNC_CTRL || serdes_rx_hdr == SYNC_DATA) begin
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// valid header
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sh_count_next = sh_count_reg + 1;
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if (&sh_count_reg) begin
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// valid count overflow, reset
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sh_count_next = 0;
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sh_invalid_count_next = 0;
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if (!sh_invalid_count_reg) begin
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rx_block_lock_next = 1'b1;
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end
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end
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end else begin
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// invalid header
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sh_count_next = sh_count_reg + 1;
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sh_invalid_count_next = sh_invalid_count_reg + 1;
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if (!rx_block_lock_reg || &sh_invalid_count_reg) begin
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// invalid count overflow, lost block lock
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sh_count_next = 0;
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sh_invalid_count_next = 0;
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rx_block_lock_next = 1'b0;
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serdes_rx_bitslip_next = 1'b1;
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slip_count_next = {SLIP_COUNT_WIDTH{1'b1}};
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end else if (&sh_count_reg) begin
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// valid count overflow, reset
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sh_count_next = 0;
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sh_invalid_count_next = 0;
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end
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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sh_count_reg <= 6'd0;
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sh_invalid_count_reg <= 4'd0;
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slip_count_reg <= 0;
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rx_block_lock_reg <= 1'b0;
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end else begin
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sh_count_reg <= sh_count_next;
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sh_invalid_count_reg <= sh_invalid_count_next;
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slip_count_reg <= slip_count_next;
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rx_block_lock_reg <= rx_block_lock_next;
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end
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serdes_rx_bitslip_reg <= serdes_rx_bitslip_next;
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end
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endmodule
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