verilog-ethernet/clock.xdc at 70912e8255e8a59118a25b7734281e4fefa0df16 - verilog-ethernet - Gitea: Git with a cup of tea

FPGA/verilog-ethernet

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Alex Forencich 795ae8a4db Add 10G example design for VCU108 board

2016-07-26 14:14:16 -04:00

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 # Clock constraints
 # internal clock groups
 set_clock_groups -asynchronous -group [get_clocks -of_objects [get_nets clk_156mhz_int]]