FPGA/verilog-ethernet
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verilog-ethernet/example/VCU1525/fpga_25g/lib
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Alex Forencich 5dc38f11b7 Use unified 10G/25G design for Alveo VCU1525 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-07-13 20:42:40 -07:00
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eth
Use unified 10G/25G design for Alveo VCU1525
2023-07-13 20:42:40 -07:00