mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-28 07:03:08 +08:00
821 lines
21 KiB
Verilog
821 lines
21 KiB
Verilog
/*
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Copyright (c) 2014-2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* FPGA top-level module
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*/
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module fpga (
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/*
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* Clock: 300MHz LVDS
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*/
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input wire clk_300mhz_p,
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input wire clk_300mhz_n,
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/*
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* GPIO
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*/
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output wire [1:0] user_led_g,
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output wire user_led_r,
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output wire [1:0] front_led,
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input wire [1:0] user_sw,
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/*
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* Ethernet: QSFP28
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*/
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output wire qsfp_0_tx_0_p,
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output wire qsfp_0_tx_0_n,
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input wire qsfp_0_rx_0_p,
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input wire qsfp_0_rx_0_n,
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output wire qsfp_0_tx_1_p,
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output wire qsfp_0_tx_1_n,
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input wire qsfp_0_rx_1_p,
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input wire qsfp_0_rx_1_n,
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output wire qsfp_0_tx_2_p,
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output wire qsfp_0_tx_2_n,
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input wire qsfp_0_rx_2_p,
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input wire qsfp_0_rx_2_n,
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output wire qsfp_0_tx_3_p,
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output wire qsfp_0_tx_3_n,
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input wire qsfp_0_rx_3_p,
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input wire qsfp_0_rx_3_n,
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input wire qsfp_0_mgt_refclk_p,
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input wire qsfp_0_mgt_refclk_n,
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input wire qsfp_0_modprs_l,
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output wire qsfp_0_sel_l,
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output wire qsfp_1_tx_0_p,
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output wire qsfp_1_tx_0_n,
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input wire qsfp_1_rx_0_p,
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input wire qsfp_1_rx_0_n,
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output wire qsfp_1_tx_1_p,
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output wire qsfp_1_tx_1_n,
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input wire qsfp_1_rx_1_p,
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input wire qsfp_1_rx_1_n,
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output wire qsfp_1_tx_2_p,
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output wire qsfp_1_tx_2_n,
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input wire qsfp_1_rx_2_p,
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input wire qsfp_1_rx_2_n,
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output wire qsfp_1_tx_3_p,
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output wire qsfp_1_tx_3_n,
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input wire qsfp_1_rx_3_p,
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input wire qsfp_1_rx_3_n,
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input wire qsfp_1_mgt_refclk_p,
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input wire qsfp_1_mgt_refclk_n,
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input wire qsfp_1_modprs_l,
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output wire qsfp_1_sel_l,
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output wire qsfp_reset_l,
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input wire qsfp_int_l
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);
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// Clock and reset
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wire clk_300mhz_ibufg;
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// Internal 125 MHz clock
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wire clk_125mhz_mmcm_out;
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wire clk_125mhz_int;
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wire rst_125mhz_int;
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// Internal 390.625 MHz clock
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wire clk_390mhz_int;
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wire rst_390mhz_int;
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wire mmcm_rst = 1'b0;
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wire mmcm_locked;
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wire mmcm_clkfb;
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IBUFGDS #(
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.DIFF_TERM("FALSE"),
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.IBUF_LOW_PWR("FALSE")
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)
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clk_300mhz_ibufg_inst (
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.O (clk_300mhz_ibufg),
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.I (clk_300mhz_p),
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.IB (clk_300mhz_n)
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);
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// MMCM instance
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// 300 MHz in, 125 MHz out
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// PFD range: 10 MHz to 500 MHz
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// VCO range: 800 MHz to 1600 MHz
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// M = 10, D = 3 sets Fvco = 1000 MHz (in range)
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// Divide by 8 to get output frequency of 125 MHz
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MMCME3_BASE #(
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.BANDWIDTH("OPTIMIZED"),
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.CLKOUT0_DIVIDE_F(8),
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT0_PHASE(0),
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.CLKOUT1_DIVIDE(1),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT1_PHASE(0),
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.CLKOUT2_DIVIDE(1),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT2_PHASE(0),
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.CLKOUT3_DIVIDE(1),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT3_PHASE(0),
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.CLKOUT4_DIVIDE(1),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT4_PHASE(0),
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.CLKOUT5_DIVIDE(1),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT5_PHASE(0),
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.CLKOUT6_DIVIDE(1),
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.CLKOUT6_DUTY_CYCLE(0.5),
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.CLKOUT6_PHASE(0),
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.CLKFBOUT_MULT_F(10),
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.CLKFBOUT_PHASE(0),
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.DIVCLK_DIVIDE(3),
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.REF_JITTER1(0.010),
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.CLKIN1_PERIOD(3.333),
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.STARTUP_WAIT("FALSE"),
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.CLKOUT4_CASCADE("FALSE")
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)
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clk_mmcm_inst (
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.CLKIN1(clk_300mhz_ibufg),
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.CLKFBIN(mmcm_clkfb),
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.RST(mmcm_rst),
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.PWRDWN(1'b0),
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.CLKOUT0(clk_125mhz_mmcm_out),
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.CLKOUT0B(),
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.CLKOUT1(),
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.CLKOUT1B(),
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.CLKOUT2(),
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.CLKOUT2B(),
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.CLKOUT3(),
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.CLKOUT3B(),
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.CLKOUT4(),
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.CLKOUT5(),
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.CLKOUT6(),
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.CLKFBOUT(mmcm_clkfb),
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.CLKFBOUTB(),
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.LOCKED(mmcm_locked)
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);
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BUFG
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clk_125mhz_bufg_inst (
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.I(clk_125mhz_mmcm_out),
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.O(clk_125mhz_int)
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);
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sync_reset #(
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.N(4)
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)
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sync_reset_125mhz_inst (
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.clk(clk_125mhz_int),
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.rst(~mmcm_locked),
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.out(rst_125mhz_int)
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);
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// GPIO
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wire [1:0] user_sw_int;
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debounce_switch #(
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.WIDTH(2),
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.N(4),
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.RATE(125000)
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)
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debounce_switch_inst (
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.clk(clk_125mhz_int),
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.rst(rst_125mhz_int),
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.in({user_sw}),
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.out({user_sw_int})
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);
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// XGMII 10G PHY
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assign qsfp_reset_l = 1'b1;
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// QSFP 0
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assign qsfp_0_sel_l = 1'b0;
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wire qsfp_0_tx_clk_0_int;
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wire qsfp_0_tx_rst_0_int;
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wire [63:0] qsfp_0_txd_0_int;
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wire [7:0] qsfp_0_txc_0_int;
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wire qsfp_0_rx_clk_0_int;
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wire qsfp_0_rx_rst_0_int;
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wire [63:0] qsfp_0_rxd_0_int;
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wire [7:0] qsfp_0_rxc_0_int;
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wire qsfp_0_tx_clk_1_int;
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wire qsfp_0_tx_rst_1_int;
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wire [63:0] qsfp_0_txd_1_int;
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wire [7:0] qsfp_0_txc_1_int;
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wire qsfp_0_rx_clk_1_int;
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wire qsfp_0_rx_rst_1_int;
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wire [63:0] qsfp_0_rxd_1_int;
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wire [7:0] qsfp_0_rxc_1_int;
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wire qsfp_0_tx_clk_2_int;
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wire qsfp_0_tx_rst_2_int;
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wire [63:0] qsfp_0_txd_2_int;
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wire [7:0] qsfp_0_txc_2_int;
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wire qsfp_0_rx_clk_2_int;
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wire qsfp_0_rx_rst_2_int;
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wire [63:0] qsfp_0_rxd_2_int;
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wire [7:0] qsfp_0_rxc_2_int;
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wire qsfp_0_tx_clk_3_int;
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wire qsfp_0_tx_rst_3_int;
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wire [63:0] qsfp_0_txd_3_int;
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wire [7:0] qsfp_0_txc_3_int;
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wire qsfp_0_rx_clk_3_int;
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wire qsfp_0_rx_rst_3_int;
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wire [63:0] qsfp_0_rxd_3_int;
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wire [7:0] qsfp_0_rxc_3_int;
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assign clk_390mhz_int = qsfp_0_tx_clk_0_int;
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assign rst_390mhz_int = qsfp_0_tx_rst_0_int;
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wire qsfp_0_rx_block_lock_0;
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wire qsfp_0_rx_block_lock_1;
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wire qsfp_0_rx_block_lock_2;
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wire qsfp_0_rx_block_lock_3;
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wire qsfp_0_mgt_refclk;
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IBUFDS_GTE4 ibufds_gte4_qsfp_0_mgt_refclk_inst (
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.I (qsfp_0_mgt_refclk_p),
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.IB (qsfp_0_mgt_refclk_n),
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.CEB (1'b0),
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.O (qsfp_0_mgt_refclk),
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.ODIV2 ()
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);
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wire qsfp_0_qpll0lock;
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wire qsfp_0_qpll0outclk;
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wire qsfp_0_qpll0outrefclk;
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eth_xcvr_phy_wrapper #(
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.HAS_COMMON(1),
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.TX_SERDES_PIPELINE(2),
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.RX_SERDES_PIPELINE(2),
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.COUNT_125US(125000/2.56)
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)
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qsfp_0_phy_0_inst (
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.xcvr_ctrl_clk(clk_125mhz_int),
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.xcvr_ctrl_rst(rst_125mhz_int),
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// Common
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.xcvr_gtpowergood_out(),
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// PLL out
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.xcvr_gtrefclk00_in(qsfp_0_mgt_refclk),
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.xcvr_qpll0lock_out(qsfp_0_qpll0lock),
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.xcvr_qpll0outclk_out(qsfp_0_qpll0outclk),
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.xcvr_qpll0outrefclk_out(qsfp_0_qpll0outrefclk),
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// PLL in
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.xcvr_qpll0lock_in(1'b0),
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.xcvr_qpll0reset_out(),
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.xcvr_qpll0clk_in(1'b0),
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.xcvr_qpll0refclk_in(1'b0),
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// Serial data
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.xcvr_txp(qsfp_0_tx_0_p),
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.xcvr_txn(qsfp_0_tx_0_n),
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.xcvr_rxp(qsfp_0_rx_0_p),
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.xcvr_rxn(qsfp_0_rx_0_n),
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// PHY connections
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.phy_tx_clk(qsfp_0_tx_clk_0_int),
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.phy_tx_rst(qsfp_0_tx_rst_0_int),
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.phy_xgmii_txd(qsfp_0_txd_0_int),
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.phy_xgmii_txc(qsfp_0_txc_0_int),
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.phy_rx_clk(qsfp_0_rx_clk_0_int),
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.phy_rx_rst(qsfp_0_rx_rst_0_int),
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.phy_xgmii_rxd(qsfp_0_rxd_0_int),
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.phy_xgmii_rxc(qsfp_0_rxc_0_int),
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.phy_tx_bad_block(),
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.phy_rx_error_count(),
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.phy_rx_bad_block(),
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.phy_rx_sequence_error(),
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.phy_rx_block_lock(qsfp_0_rx_block_lock_0),
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.phy_rx_high_ber(),
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.phy_cfg_tx_prbs31_enable(1'b0),
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.phy_cfg_rx_prbs31_enable(1'b0)
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);
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eth_xcvr_phy_wrapper #(
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.HAS_COMMON(0),
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.TX_SERDES_PIPELINE(2),
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.RX_SERDES_PIPELINE(2),
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.COUNT_125US(125000/2.56)
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)
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qsfp_0_phy_1_inst (
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.xcvr_ctrl_clk(clk_125mhz_int),
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.xcvr_ctrl_rst(rst_125mhz_int),
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// Common
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.xcvr_gtpowergood_out(),
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// PLL out
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.xcvr_gtrefclk00_in(1'b0),
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.xcvr_qpll0lock_out(),
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.xcvr_qpll0outclk_out(),
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.xcvr_qpll0outrefclk_out(),
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// PLL in
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.xcvr_qpll0lock_in(qsfp_0_qpll0lock),
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.xcvr_qpll0reset_out(),
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.xcvr_qpll0clk_in(qsfp_0_qpll0outclk),
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.xcvr_qpll0refclk_in(qsfp_0_qpll0outrefclk),
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// Serial data
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.xcvr_txp(qsfp_0_tx_1_p),
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.xcvr_txn(qsfp_0_tx_1_n),
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.xcvr_rxp(qsfp_0_rx_1_p),
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.xcvr_rxn(qsfp_0_rx_1_n),
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// PHY connections
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.phy_tx_clk(qsfp_0_tx_clk_1_int),
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.phy_tx_rst(qsfp_0_tx_rst_1_int),
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.phy_xgmii_txd(qsfp_0_txd_1_int),
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.phy_xgmii_txc(qsfp_0_txc_1_int),
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.phy_rx_clk(qsfp_0_rx_clk_1_int),
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.phy_rx_rst(qsfp_0_rx_rst_1_int),
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.phy_xgmii_rxd(qsfp_0_rxd_1_int),
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.phy_xgmii_rxc(qsfp_0_rxc_1_int),
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.phy_tx_bad_block(),
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.phy_rx_error_count(),
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.phy_rx_bad_block(),
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.phy_rx_sequence_error(),
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.phy_rx_block_lock(qsfp_0_rx_block_lock_1),
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.phy_rx_high_ber(),
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.phy_cfg_tx_prbs31_enable(1'b0),
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.phy_cfg_rx_prbs31_enable(1'b0)
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);
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eth_xcvr_phy_wrapper #(
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.HAS_COMMON(0),
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.TX_SERDES_PIPELINE(2),
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.RX_SERDES_PIPELINE(2),
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.COUNT_125US(125000/2.56)
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)
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qsfp_0_phy_2_inst (
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.xcvr_ctrl_clk(clk_125mhz_int),
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.xcvr_ctrl_rst(rst_125mhz_int),
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// Common
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.xcvr_gtpowergood_out(),
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// PLL out
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.xcvr_gtrefclk00_in(1'b0),
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.xcvr_qpll0lock_out(),
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.xcvr_qpll0outclk_out(),
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.xcvr_qpll0outrefclk_out(),
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// PLL in
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.xcvr_qpll0lock_in(qsfp_0_qpll0lock),
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.xcvr_qpll0reset_out(),
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.xcvr_qpll0clk_in(qsfp_0_qpll0outclk),
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.xcvr_qpll0refclk_in(qsfp_0_qpll0outrefclk),
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// Serial data
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.xcvr_txp(qsfp_0_tx_2_p),
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.xcvr_txn(qsfp_0_tx_2_n),
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.xcvr_rxp(qsfp_0_rx_2_p),
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.xcvr_rxn(qsfp_0_rx_2_n),
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// PHY connections
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.phy_tx_clk(qsfp_0_tx_clk_2_int),
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.phy_tx_rst(qsfp_0_tx_rst_2_int),
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.phy_xgmii_txd(qsfp_0_txd_2_int),
|
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.phy_xgmii_txc(qsfp_0_txc_2_int),
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.phy_rx_clk(qsfp_0_rx_clk_2_int),
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.phy_rx_rst(qsfp_0_rx_rst_2_int),
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.phy_xgmii_rxd(qsfp_0_rxd_2_int),
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.phy_xgmii_rxc(qsfp_0_rxc_2_int),
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.phy_tx_bad_block(),
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.phy_rx_error_count(),
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.phy_rx_bad_block(),
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.phy_rx_sequence_error(),
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.phy_rx_block_lock(qsfp_0_rx_block_lock_2),
|
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.phy_rx_high_ber(),
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.phy_cfg_tx_prbs31_enable(1'b0),
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.phy_cfg_rx_prbs31_enable(1'b0)
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);
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eth_xcvr_phy_wrapper #(
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.HAS_COMMON(0),
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.TX_SERDES_PIPELINE(2),
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.RX_SERDES_PIPELINE(2),
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.COUNT_125US(125000/2.56)
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)
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qsfp_0_phy_3_inst (
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.xcvr_ctrl_clk(clk_125mhz_int),
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.xcvr_ctrl_rst(rst_125mhz_int),
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// Common
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.xcvr_gtpowergood_out(),
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// PLL out
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.xcvr_gtrefclk00_in(1'b0),
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.xcvr_qpll0lock_out(),
|
|
.xcvr_qpll0outclk_out(),
|
|
.xcvr_qpll0outrefclk_out(),
|
|
|
|
// PLL in
|
|
.xcvr_qpll0lock_in(qsfp_0_qpll0lock),
|
|
.xcvr_qpll0reset_out(),
|
|
.xcvr_qpll0clk_in(qsfp_0_qpll0outclk),
|
|
.xcvr_qpll0refclk_in(qsfp_0_qpll0outrefclk),
|
|
|
|
// Serial data
|
|
.xcvr_txp(qsfp_0_tx_3_p),
|
|
.xcvr_txn(qsfp_0_tx_3_n),
|
|
.xcvr_rxp(qsfp_0_rx_3_p),
|
|
.xcvr_rxn(qsfp_0_rx_3_n),
|
|
|
|
// PHY connections
|
|
.phy_tx_clk(qsfp_0_tx_clk_3_int),
|
|
.phy_tx_rst(qsfp_0_tx_rst_3_int),
|
|
.phy_xgmii_txd(qsfp_0_txd_3_int),
|
|
.phy_xgmii_txc(qsfp_0_txc_3_int),
|
|
.phy_rx_clk(qsfp_0_rx_clk_3_int),
|
|
.phy_rx_rst(qsfp_0_rx_rst_3_int),
|
|
.phy_xgmii_rxd(qsfp_0_rxd_3_int),
|
|
.phy_xgmii_rxc(qsfp_0_rxc_3_int),
|
|
.phy_tx_bad_block(),
|
|
.phy_rx_error_count(),
|
|
.phy_rx_bad_block(),
|
|
.phy_rx_sequence_error(),
|
|
.phy_rx_block_lock(qsfp_0_rx_block_lock_3),
|
|
.phy_rx_high_ber(),
|
|
.phy_cfg_tx_prbs31_enable(1'b0),
|
|
.phy_cfg_rx_prbs31_enable(1'b0)
|
|
);
|
|
|
|
// QSFP 1
|
|
assign qsfp_1_sel_l = 1'b0;
|
|
|
|
wire qsfp_1_tx_clk_0_int;
|
|
wire qsfp_1_tx_rst_0_int;
|
|
wire [63:0] qsfp_1_txd_0_int;
|
|
wire [7:0] qsfp_1_txc_0_int;
|
|
wire qsfp_1_rx_clk_0_int;
|
|
wire qsfp_1_rx_rst_0_int;
|
|
wire [63:0] qsfp_1_rxd_0_int;
|
|
wire [7:0] qsfp_1_rxc_0_int;
|
|
wire qsfp_1_tx_clk_1_int;
|
|
wire qsfp_1_tx_rst_1_int;
|
|
wire [63:0] qsfp_1_txd_1_int;
|
|
wire [7:0] qsfp_1_txc_1_int;
|
|
wire qsfp_1_rx_clk_1_int;
|
|
wire qsfp_1_rx_rst_1_int;
|
|
wire [63:0] qsfp_1_rxd_1_int;
|
|
wire [7:0] qsfp_1_rxc_1_int;
|
|
wire qsfp_1_tx_clk_2_int;
|
|
wire qsfp_1_tx_rst_2_int;
|
|
wire [63:0] qsfp_1_txd_2_int;
|
|
wire [7:0] qsfp_1_txc_2_int;
|
|
wire qsfp_1_rx_clk_2_int;
|
|
wire qsfp_1_rx_rst_2_int;
|
|
wire [63:0] qsfp_1_rxd_2_int;
|
|
wire [7:0] qsfp_1_rxc_2_int;
|
|
wire qsfp_1_tx_clk_3_int;
|
|
wire qsfp_1_tx_rst_3_int;
|
|
wire [63:0] qsfp_1_txd_3_int;
|
|
wire [7:0] qsfp_1_txc_3_int;
|
|
wire qsfp_1_rx_clk_3_int;
|
|
wire qsfp_1_rx_rst_3_int;
|
|
wire [63:0] qsfp_1_rxd_3_int;
|
|
wire [7:0] qsfp_1_rxc_3_int;
|
|
|
|
wire qsfp_1_rx_block_lock_0;
|
|
wire qsfp_1_rx_block_lock_1;
|
|
wire qsfp_1_rx_block_lock_2;
|
|
wire qsfp_1_rx_block_lock_3;
|
|
|
|
wire qsfp_1_mgt_refclk;
|
|
|
|
IBUFDS_GTE4 ibufds_gte4_qsfp_1_mgt_refclk_inst (
|
|
.I (qsfp_1_mgt_refclk_p),
|
|
.IB (qsfp_1_mgt_refclk_n),
|
|
.CEB (1'b0),
|
|
.O (qsfp_1_mgt_refclk),
|
|
.ODIV2 ()
|
|
);
|
|
|
|
wire qsfp_1_qpll0lock;
|
|
wire qsfp_1_qpll0outclk;
|
|
wire qsfp_1_qpll0outrefclk;
|
|
|
|
eth_xcvr_phy_wrapper #(
|
|
.HAS_COMMON(1),
|
|
.TX_SERDES_PIPELINE(2),
|
|
.RX_SERDES_PIPELINE(2),
|
|
.COUNT_125US(125000/2.56)
|
|
)
|
|
qsfp_1_phy_0_inst (
|
|
.xcvr_ctrl_clk(clk_125mhz_int),
|
|
.xcvr_ctrl_rst(rst_125mhz_int),
|
|
|
|
// Common
|
|
.xcvr_gtpowergood_out(),
|
|
|
|
// PLL out
|
|
.xcvr_gtrefclk00_in(qsfp_1_mgt_refclk),
|
|
.xcvr_qpll0lock_out(qsfp_1_qpll0lock),
|
|
.xcvr_qpll0outclk_out(qsfp_1_qpll0outclk),
|
|
.xcvr_qpll0outrefclk_out(qsfp_1_qpll0outrefclk),
|
|
|
|
// PLL in
|
|
.xcvr_qpll0lock_in(1'b0),
|
|
.xcvr_qpll0reset_out(),
|
|
.xcvr_qpll0clk_in(1'b0),
|
|
.xcvr_qpll0refclk_in(1'b0),
|
|
|
|
// Serial data
|
|
.xcvr_txp(qsfp_1_tx_0_p),
|
|
.xcvr_txn(qsfp_1_tx_0_n),
|
|
.xcvr_rxp(qsfp_1_rx_0_p),
|
|
.xcvr_rxn(qsfp_1_rx_0_n),
|
|
|
|
// PHY connections
|
|
.phy_tx_clk(qsfp_1_tx_clk_0_int),
|
|
.phy_tx_rst(qsfp_1_tx_rst_0_int),
|
|
.phy_xgmii_txd(qsfp_1_txd_0_int),
|
|
.phy_xgmii_txc(qsfp_1_txc_0_int),
|
|
.phy_rx_clk(qsfp_1_rx_clk_0_int),
|
|
.phy_rx_rst(qsfp_1_rx_rst_0_int),
|
|
.phy_xgmii_rxd(qsfp_1_rxd_0_int),
|
|
.phy_xgmii_rxc(qsfp_1_rxc_0_int),
|
|
.phy_tx_bad_block(),
|
|
.phy_rx_error_count(),
|
|
.phy_rx_bad_block(),
|
|
.phy_rx_sequence_error(),
|
|
.phy_rx_block_lock(qsfp_1_rx_block_lock_0),
|
|
.phy_rx_high_ber(),
|
|
.phy_cfg_tx_prbs31_enable(1'b0),
|
|
.phy_cfg_rx_prbs31_enable(1'b0)
|
|
);
|
|
|
|
eth_xcvr_phy_wrapper #(
|
|
.HAS_COMMON(0),
|
|
.TX_SERDES_PIPELINE(2),
|
|
.RX_SERDES_PIPELINE(2),
|
|
.COUNT_125US(125000/2.56)
|
|
)
|
|
qsfp_1_phy_1_inst (
|
|
.xcvr_ctrl_clk(clk_125mhz_int),
|
|
.xcvr_ctrl_rst(rst_125mhz_int),
|
|
|
|
// Common
|
|
.xcvr_gtpowergood_out(),
|
|
|
|
// PLL out
|
|
.xcvr_gtrefclk00_in(1'b0),
|
|
.xcvr_qpll0lock_out(),
|
|
.xcvr_qpll0outclk_out(),
|
|
.xcvr_qpll0outrefclk_out(),
|
|
|
|
// PLL in
|
|
.xcvr_qpll0lock_in(qsfp_1_qpll0lock),
|
|
.xcvr_qpll0reset_out(),
|
|
.xcvr_qpll0clk_in(qsfp_1_qpll0outclk),
|
|
.xcvr_qpll0refclk_in(qsfp_1_qpll0outrefclk),
|
|
|
|
// Serial data
|
|
.xcvr_txp(qsfp_1_tx_1_p),
|
|
.xcvr_txn(qsfp_1_tx_1_n),
|
|
.xcvr_rxp(qsfp_1_rx_1_p),
|
|
.xcvr_rxn(qsfp_1_rx_1_n),
|
|
|
|
// PHY connections
|
|
.phy_tx_clk(qsfp_1_tx_clk_1_int),
|
|
.phy_tx_rst(qsfp_1_tx_rst_1_int),
|
|
.phy_xgmii_txd(qsfp_1_txd_1_int),
|
|
.phy_xgmii_txc(qsfp_1_txc_1_int),
|
|
.phy_rx_clk(qsfp_1_rx_clk_1_int),
|
|
.phy_rx_rst(qsfp_1_rx_rst_1_int),
|
|
.phy_xgmii_rxd(qsfp_1_rxd_1_int),
|
|
.phy_xgmii_rxc(qsfp_1_rxc_1_int),
|
|
.phy_tx_bad_block(),
|
|
.phy_rx_error_count(),
|
|
.phy_rx_bad_block(),
|
|
.phy_rx_sequence_error(),
|
|
.phy_rx_block_lock(qsfp_1_rx_block_lock_1),
|
|
.phy_rx_high_ber(),
|
|
.phy_cfg_tx_prbs31_enable(1'b0),
|
|
.phy_cfg_rx_prbs31_enable(1'b0)
|
|
);
|
|
|
|
eth_xcvr_phy_wrapper #(
|
|
.HAS_COMMON(0),
|
|
.TX_SERDES_PIPELINE(2),
|
|
.RX_SERDES_PIPELINE(2),
|
|
.COUNT_125US(125000/2.56)
|
|
)
|
|
qsfp_1_phy_2_inst (
|
|
.xcvr_ctrl_clk(clk_125mhz_int),
|
|
.xcvr_ctrl_rst(rst_125mhz_int),
|
|
|
|
// Common
|
|
.xcvr_gtpowergood_out(),
|
|
|
|
// PLL out
|
|
.xcvr_gtrefclk00_in(1'b0),
|
|
.xcvr_qpll0lock_out(),
|
|
.xcvr_qpll0outclk_out(),
|
|
.xcvr_qpll0outrefclk_out(),
|
|
|
|
// PLL in
|
|
.xcvr_qpll0lock_in(qsfp_1_qpll0lock),
|
|
.xcvr_qpll0reset_out(),
|
|
.xcvr_qpll0clk_in(qsfp_1_qpll0outclk),
|
|
.xcvr_qpll0refclk_in(qsfp_1_qpll0outrefclk),
|
|
|
|
// Serial data
|
|
.xcvr_txp(qsfp_1_tx_2_p),
|
|
.xcvr_txn(qsfp_1_tx_2_n),
|
|
.xcvr_rxp(qsfp_1_rx_2_p),
|
|
.xcvr_rxn(qsfp_1_rx_2_n),
|
|
|
|
// PHY connections
|
|
.phy_tx_clk(qsfp_1_tx_clk_2_int),
|
|
.phy_tx_rst(qsfp_1_tx_rst_2_int),
|
|
.phy_xgmii_txd(qsfp_1_txd_2_int),
|
|
.phy_xgmii_txc(qsfp_1_txc_2_int),
|
|
.phy_rx_clk(qsfp_1_rx_clk_2_int),
|
|
.phy_rx_rst(qsfp_1_rx_rst_2_int),
|
|
.phy_xgmii_rxd(qsfp_1_rxd_2_int),
|
|
.phy_xgmii_rxc(qsfp_1_rxc_2_int),
|
|
.phy_tx_bad_block(),
|
|
.phy_rx_error_count(),
|
|
.phy_rx_bad_block(),
|
|
.phy_rx_sequence_error(),
|
|
.phy_rx_block_lock(qsfp_1_rx_block_lock_2),
|
|
.phy_rx_high_ber(),
|
|
.phy_cfg_tx_prbs31_enable(1'b0),
|
|
.phy_cfg_rx_prbs31_enable(1'b0)
|
|
);
|
|
|
|
eth_xcvr_phy_wrapper #(
|
|
.HAS_COMMON(0),
|
|
.TX_SERDES_PIPELINE(2),
|
|
.RX_SERDES_PIPELINE(2),
|
|
.COUNT_125US(125000/2.56)
|
|
)
|
|
qsfp_1_phy_3_inst (
|
|
.xcvr_ctrl_clk(clk_125mhz_int),
|
|
.xcvr_ctrl_rst(rst_125mhz_int),
|
|
|
|
// Common
|
|
.xcvr_gtpowergood_out(),
|
|
|
|
// PLL out
|
|
.xcvr_gtrefclk00_in(1'b0),
|
|
.xcvr_qpll0lock_out(),
|
|
.xcvr_qpll0outclk_out(),
|
|
.xcvr_qpll0outrefclk_out(),
|
|
|
|
// PLL in
|
|
.xcvr_qpll0lock_in(qsfp_1_qpll0lock),
|
|
.xcvr_qpll0reset_out(),
|
|
.xcvr_qpll0clk_in(qsfp_1_qpll0outclk),
|
|
.xcvr_qpll0refclk_in(qsfp_1_qpll0outrefclk),
|
|
|
|
// Serial data
|
|
.xcvr_txp(qsfp_1_tx_3_p),
|
|
.xcvr_txn(qsfp_1_tx_3_n),
|
|
.xcvr_rxp(qsfp_1_rx_3_p),
|
|
.xcvr_rxn(qsfp_1_rx_3_n),
|
|
|
|
// PHY connections
|
|
.phy_tx_clk(qsfp_1_tx_clk_3_int),
|
|
.phy_tx_rst(qsfp_1_tx_rst_3_int),
|
|
.phy_xgmii_txd(qsfp_1_txd_3_int),
|
|
.phy_xgmii_txc(qsfp_1_txc_3_int),
|
|
.phy_rx_clk(qsfp_1_rx_clk_3_int),
|
|
.phy_rx_rst(qsfp_1_rx_rst_3_int),
|
|
.phy_xgmii_rxd(qsfp_1_rxd_3_int),
|
|
.phy_xgmii_rxc(qsfp_1_rxc_3_int),
|
|
.phy_tx_bad_block(),
|
|
.phy_rx_error_count(),
|
|
.phy_rx_bad_block(),
|
|
.phy_rx_sequence_error(),
|
|
.phy_rx_block_lock(qsfp_1_rx_block_lock_3),
|
|
.phy_rx_high_ber(),
|
|
.phy_cfg_tx_prbs31_enable(1'b0),
|
|
.phy_cfg_rx_prbs31_enable(1'b0)
|
|
);
|
|
|
|
assign front_led[0] = qsfp_0_rx_block_lock_0;
|
|
assign front_led[1] = qsfp_1_rx_block_lock_0;
|
|
|
|
fpga_core
|
|
core_inst (
|
|
/*
|
|
* Clock: 390.625 MHz
|
|
* Synchronous reset
|
|
*/
|
|
.clk(clk_390mhz_int),
|
|
.rst(rst_390mhz_int),
|
|
/*
|
|
* GPIO
|
|
*/
|
|
.user_led_g(user_led_g),
|
|
.user_led_r(user_led_r),
|
|
//.front_led(front_led),
|
|
.user_sw(user_sw_int),
|
|
|
|
/*
|
|
* Ethernet: QSFP28
|
|
*/
|
|
.qsfp_0_tx_clk_0(qsfp_0_tx_clk_0_int),
|
|
.qsfp_0_tx_rst_0(qsfp_0_tx_rst_0_int),
|
|
.qsfp_0_txd_0(qsfp_0_txd_0_int),
|
|
.qsfp_0_txc_0(qsfp_0_txc_0_int),
|
|
.qsfp_0_rx_clk_0(qsfp_0_rx_clk_0_int),
|
|
.qsfp_0_rx_rst_0(qsfp_0_rx_rst_0_int),
|
|
.qsfp_0_rxd_0(qsfp_0_rxd_0_int),
|
|
.qsfp_0_rxc_0(qsfp_0_rxc_0_int),
|
|
.qsfp_0_tx_clk_1(qsfp_0_tx_clk_1_int),
|
|
.qsfp_0_tx_rst_1(qsfp_0_tx_rst_1_int),
|
|
.qsfp_0_txd_1(qsfp_0_txd_1_int),
|
|
.qsfp_0_txc_1(qsfp_0_txc_1_int),
|
|
.qsfp_0_rx_clk_1(qsfp_0_rx_clk_1_int),
|
|
.qsfp_0_rx_rst_1(qsfp_0_rx_rst_1_int),
|
|
.qsfp_0_rxd_1(qsfp_0_rxd_1_int),
|
|
.qsfp_0_rxc_1(qsfp_0_rxc_1_int),
|
|
.qsfp_0_tx_clk_2(qsfp_0_tx_clk_2_int),
|
|
.qsfp_0_tx_rst_2(qsfp_0_tx_rst_2_int),
|
|
.qsfp_0_txd_2(qsfp_0_txd_2_int),
|
|
.qsfp_0_txc_2(qsfp_0_txc_2_int),
|
|
.qsfp_0_rx_clk_2(qsfp_0_rx_clk_2_int),
|
|
.qsfp_0_rx_rst_2(qsfp_0_rx_rst_2_int),
|
|
.qsfp_0_rxd_2(qsfp_0_rxd_2_int),
|
|
.qsfp_0_rxc_2(qsfp_0_rxc_2_int),
|
|
.qsfp_0_tx_clk_3(qsfp_0_tx_clk_3_int),
|
|
.qsfp_0_tx_rst_3(qsfp_0_tx_rst_3_int),
|
|
.qsfp_0_txd_3(qsfp_0_txd_3_int),
|
|
.qsfp_0_txc_3(qsfp_0_txc_3_int),
|
|
.qsfp_0_rx_clk_3(qsfp_0_rx_clk_3_int),
|
|
.qsfp_0_rx_rst_3(qsfp_0_rx_rst_3_int),
|
|
.qsfp_0_rxd_3(qsfp_0_rxd_3_int),
|
|
.qsfp_0_rxc_3(qsfp_0_rxc_3_int),
|
|
.qsfp_1_tx_clk_0(qsfp_1_tx_clk_0_int),
|
|
.qsfp_1_tx_rst_0(qsfp_1_tx_rst_0_int),
|
|
.qsfp_1_txd_0(qsfp_1_txd_0_int),
|
|
.qsfp_1_txc_0(qsfp_1_txc_0_int),
|
|
.qsfp_1_rx_clk_0(qsfp_1_rx_clk_0_int),
|
|
.qsfp_1_rx_rst_0(qsfp_1_rx_rst_0_int),
|
|
.qsfp_1_rxd_0(qsfp_1_rxd_0_int),
|
|
.qsfp_1_rxc_0(qsfp_1_rxc_0_int),
|
|
.qsfp_1_tx_clk_1(qsfp_1_tx_clk_1_int),
|
|
.qsfp_1_tx_rst_1(qsfp_1_tx_rst_1_int),
|
|
.qsfp_1_txd_1(qsfp_1_txd_1_int),
|
|
.qsfp_1_txc_1(qsfp_1_txc_1_int),
|
|
.qsfp_1_rx_clk_1(qsfp_1_rx_clk_1_int),
|
|
.qsfp_1_rx_rst_1(qsfp_1_rx_rst_1_int),
|
|
.qsfp_1_rxd_1(qsfp_1_rxd_1_int),
|
|
.qsfp_1_rxc_1(qsfp_1_rxc_1_int),
|
|
.qsfp_1_tx_clk_2(qsfp_1_tx_clk_2_int),
|
|
.qsfp_1_tx_rst_2(qsfp_1_tx_rst_2_int),
|
|
.qsfp_1_txd_2(qsfp_1_txd_2_int),
|
|
.qsfp_1_txc_2(qsfp_1_txc_2_int),
|
|
.qsfp_1_rx_clk_2(qsfp_1_rx_clk_2_int),
|
|
.qsfp_1_rx_rst_2(qsfp_1_rx_rst_2_int),
|
|
.qsfp_1_rxd_2(qsfp_1_rxd_2_int),
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.qsfp_1_rxc_2(qsfp_1_rxc_2_int),
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.qsfp_1_tx_clk_3(qsfp_1_tx_clk_3_int),
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.qsfp_1_tx_rst_3(qsfp_1_tx_rst_3_int),
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.qsfp_1_txd_3(qsfp_1_txd_3_int),
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.qsfp_1_txc_3(qsfp_1_txc_3_int),
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.qsfp_1_rx_clk_3(qsfp_1_rx_clk_3_int),
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.qsfp_1_rx_rst_3(qsfp_1_rx_rst_3_int),
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.qsfp_1_rxd_3(qsfp_1_rxd_3_int),
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.qsfp_1_rxc_3(qsfp_1_rxc_3_int)
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);
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endmodule
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`resetall
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