FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-14 06:43:18 +08:00
Code Issues Projects Releases Wiki Activity
verilog-ethernet/rtl
History
Alex Forencich 77bae7a77e Add PTP clock CDC module and testbench
2019-07-15 15:16:17 -07:00
..
arp_64.v
Fix constants
2019-04-03 11:48:09 -07:00
arp_cache.v
Implement ARP cache clear
2019-06-14 00:01:13 -07:00
arp_eth_rx_64.v
Assert header ready earlier if possible
2018-11-07 23:10:07 -08:00
arp_eth_rx.v
Assert header ready earlier if possible
2018-11-07 23:10:07 -08:00
arp_eth_tx_64.v
Fix widths
2019-03-14 14:44:00 -07:00
arp_eth_tx.v
Assert header ready earlier if possible
2018-11-07 23:10:07 -08:00
arp.v
Fix constants
2019-04-03 11:48:09 -07:00
axis_baser_rx_64.v
CRC handling logic optimizations
2019-06-20 18:10:53 -07:00
axis_baser_tx_64.v
Make use of blocking statements consistent
2019-06-15 16:56:45 -07:00
axis_eth_fcs_64.v
Rename ports
2018-11-07 22:35:06 -08:00
axis_eth_fcs_check_64.v
Rename ports
2018-11-07 22:35:06 -08:00
axis_eth_fcs_check.v
Rename ports
2018-11-07 22:35:06 -08:00
axis_eth_fcs_insert_64.v
Rename ports
2018-11-07 22:35:06 -08:00
axis_eth_fcs_insert.v
Rename ports
2018-11-07 22:35:06 -08:00
axis_eth_fcs.v
Rename ports
2018-11-07 22:35:06 -08:00
axis_gmii_rx.v
Add PTP timestamp capture logic to MACs
2019-06-07 16:38:36 -07:00
axis_gmii_tx.v
Decouple transmit PTP tag enable and transmit PTP timestamp enable
2019-06-09 22:03:24 -07:00
axis_xgmii_rx_32.v
CRC handling logic optimizations
2019-06-16 17:39:28 -07:00
axis_xgmii_rx_64.v
CRC handling logic optimizations
2019-06-16 17:39:28 -07:00
axis_xgmii_tx_32.v
Decouple transmit PTP tag enable and transmit PTP timestamp enable
2019-06-09 22:03:24 -07:00
axis_xgmii_tx_64.v
Make use of blocking statements consistent
2019-06-15 16:56:45 -07:00
eth_arb_mux.v
Convert generated eth_arb_mux to verilog parametrized module
2018-10-31 21:42:28 -07:00
eth_axis_rx_64.v
shift_axis_extra_cycle timing optimization
2019-06-16 19:57:52 -07:00
eth_axis_rx.v
Rename ports
2018-11-07 22:35:06 -08:00
eth_axis_tx_64.v
shift_axis_extra_cycle timing optimization
2019-06-16 19:57:52 -07:00
eth_axis_tx.v
Rename ports
2018-11-07 22:35:06 -08:00
eth_demux.v
Convert generated eth_demux to verilog parametrized module
2018-11-02 00:23:31 -07:00
eth_mac_1g_fifo.v
Rename tx_sync regs
2019-03-28 16:27:33 -07:00
eth_mac_1g_gmii_fifo.v
Rename tx_sync regs
2019-03-28 16:27:33 -07:00
eth_mac_1g_gmii.v
Prevent SRL inference in synchronizers
2019-03-28 12:36:32 -07:00
eth_mac_1g_rgmii_fifo.v
Rename tx_sync regs
2019-03-28 16:27:33 -07:00
eth_mac_1g_rgmii.v
Prevent SRL inference in synchronizers
2019-03-28 12:36:32 -07:00
eth_mac_1g.v
Decouple transmit PTP tag enable and transmit PTP timestamp enable
2019-06-09 22:03:24 -07:00
eth_mac_10g_fifo.v
Rename tx_sync regs
2019-03-28 16:27:33 -07:00
eth_mac_10g.v
Decouple transmit PTP tag enable and transmit PTP timestamp enable
2019-06-09 22:03:24 -07:00
eth_mac_mii_fifo.v
Add MII PHY interface, MAC wrappers, and testbenches
2019-03-28 19:18:03 -07:00
eth_mac_mii.v
Add MII PHY interface, MAC wrappers, and testbenches
2019-03-28 19:18:03 -07:00
eth_mac_phy_10g_fifo.v
Add configurable serdes pipeline register chain
2019-06-19 00:57:28 -07:00
eth_mac_phy_10g_rx.v
Add configurable serdes pipeline register chain
2019-06-19 00:57:28 -07:00
eth_mac_phy_10g_tx.v
Add configurable serdes pipeline register chain
2019-06-19 00:57:28 -07:00
eth_mac_phy_10g.v
Add configurable serdes pipeline register chain
2019-06-19 00:57:28 -07:00
eth_mux.v
Convert generated eth_mux to verilog parametrized module
2018-10-31 15:48:12 -07:00
eth_phy_10g_rx_ber_mon.v
Add 10G Ethernet PHY modules and testbenches
2019-01-16 18:00:56 -08:00
eth_phy_10g_rx_frame_sync.v
Add 10G Ethernet PHY modules and testbenches
2019-01-16 18:00:56 -08:00
eth_phy_10g_rx_if.v
Add configurable serdes pipeline register chain
2019-06-19 00:57:28 -07:00
eth_phy_10g_rx.v
Add configurable serdes pipeline register chain
2019-06-19 00:57:28 -07:00
eth_phy_10g_tx_if.v
Add configurable serdes pipeline register chain
2019-06-19 00:57:28 -07:00
eth_phy_10g_tx.v
Add configurable serdes pipeline register chain
2019-06-19 00:57:28 -07:00
eth_phy_10g.v
Add configurable serdes pipeline register chain
2019-06-19 00:57:28 -07:00
gmii_phy_if.v
Happy new year
2018-02-26 12:50:51 -08:00
iddr.v
Add documentation
2018-06-04 18:21:55 -07:00
ip_64.v
Rename ports
2018-11-07 22:35:06 -08:00
ip_arb_mux.v
Convert generated ip_arb_mux to verilog parametrized module
2018-11-01 00:40:09 -07:00
ip_complete_64.v
Rename ports
2018-11-07 22:35:06 -08:00
ip_complete.v
Rename ports
2018-11-07 22:35:06 -08:00
ip_demux.v
Convert generated ip_demux to verilog parametrized module
2018-11-02 00:25:23 -07:00
ip_eth_rx_64.v
More critical path optimizations
2019-06-19 15:06:55 -07:00
ip_eth_rx.v
Rework pointer handling to improve timing
2019-06-16 23:53:26 -07:00
ip_eth_tx_64.v
More critical path optimizations
2019-06-19 15:06:55 -07:00
ip_eth_tx.v
Rework pointer handling to improve timing
2019-06-16 23:53:26 -07:00
ip_mux.v
Convert generated ip_mux to verilog parametrized module
2018-10-31 18:08:39 -07:00
ip.v
Rename ports
2018-11-07 22:35:06 -08:00
lfsr.v
Happy new year
2018-02-26 12:50:51 -08:00
mii_phy_if.v
Add MII PHY interface, MAC wrappers, and testbenches
2019-03-28 19:18:03 -07:00
oddr.v
Add documentation
2018-06-04 18:21:55 -07:00
ptp_clock_cdc.v
Add PTP clock CDC module and testbench
2019-07-15 15:16:17 -07:00
ptp_clock.v
Add PTP clock module and testbench
2019-06-03 19:00:28 -07:00
ptp_perout.v
Add PTP perout module and testbench
2019-06-27 01:30:18 -07:00
rgmii_phy_if.v
Happy new year
2018-02-26 12:50:51 -08:00
ssio_ddr_in_diff.v
Happy new year
2018-02-26 12:50:51 -08:00
ssio_ddr_in.v
Happy new year
2018-02-26 12:50:51 -08:00
ssio_ddr_out_diff.v
Happy new year
2018-02-26 12:50:51 -08:00
ssio_ddr_out.v
Happy new year
2018-02-26 12:50:51 -08:00
ssio_sdr_in_diff.v
Happy new year
2018-02-26 12:50:51 -08:00
ssio_sdr_in.v
Happy new year
2018-02-26 12:50:51 -08:00
ssio_sdr_out_diff.v
Happy new year
2018-02-26 12:50:51 -08:00
ssio_sdr_out.v
Happy new year
2018-02-26 12:50:51 -08:00
udp_64.v
Rename ports
2018-11-07 22:35:06 -08:00
udp_arb_mux.v
Convert generated udp_arb_mux to verilog parametrized module
2018-11-01 00:48:26 -07:00
udp_checksum_gen_64.v
Rename ports
2018-11-07 22:35:06 -08:00
udp_checksum_gen.v
Rename ports
2018-11-07 22:35:06 -08:00
udp_complete_64.v
Rename ports
2018-11-07 22:35:06 -08:00
udp_complete.v
Rename ports
2018-11-07 22:35:06 -08:00
udp_demux.v
Convert generated udp_demux to verilog parametrized module
2018-11-02 00:39:52 -07:00
udp_ip_rx_64.v
More critical path optimizations
2019-06-19 15:06:55 -07:00
udp_ip_rx.v
Rework pointer handling to improve timing
2019-06-16 23:53:26 -07:00
udp_ip_tx_64.v
More critical path optimizations
2019-06-19 15:06:55 -07:00
udp_ip_tx.v
Rework pointer handling to improve timing
2019-06-16 23:53:26 -07:00
udp_mux.v
Convert generated udp_mux to verilog parametrized module
2018-10-31 18:09:44 -07:00
udp.v
Rename ports
2018-11-07 22:35:06 -08:00
xgmii_baser_dec_64.v
Add XGMII 10GBASE-R encoder and decoder modules and testbenches
2019-01-16 17:30:07 -08:00
xgmii_baser_enc_64.v
Add XGMII 10GBASE-R encoder and decoder modules and testbenches
2019-01-16 17:30:07 -08:00
xgmii_deinterleave.v
Happy new year
2018-02-26 12:50:51 -08:00
xgmii_interleave.v
Happy new year
2018-02-26 12:50:51 -08:00