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FPGA/verilog-ethernet

mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-02-04 07:13:13 +08:00

History

Alex Forencich 786e971f40 Remove separate memory read register (it causes ISE to crash, and is not necessary for URAM inference)

Signed-off-by: Alex Forencich <alex@alexforencich.com>

2022-12-29 23:54:17 -08:00

..

Split async FIFO resets

2021-10-13 14:05:13 -07:00

Split async FIFO resets

2021-10-13 14:05:13 -07:00

Remove separate memory read register (it causes ISE to crash, and is not necessary for URAM inference)

2022-12-29 23:54:17 -08:00