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FPGA
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verilog-ethernet
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https://github.com/alexforencich/verilog-ethernet.git
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verilog-ethernet
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example
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VCU108
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fpga_1g
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rtl
History
Alex Forencich
e38ffe16b8
Adjust config vector assignment
2016-07-13 14:38:22 -04:00
..
debounce_switch.v
Add example design for VCU108 board
2016-07-05 11:52:28 -04:00
fpga_core.v
Remove unused parameter; update XDC file
2016-07-13 11:57:14 -04:00
fpga.v
Adjust config vector assignment
2016-07-13 14:38:22 -04:00
sync_reset.v
Add example design for VCU108 board
2016-07-05 11:52:28 -04:00
sync_signal.v
Add example design for VCU108 board
2016-07-05 11:52:28 -04:00
