FPGA/verilog-ethernet
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Alex Forencich 7a0e88ffea Update vivado.mk 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-01-13 14:57:46 -08:00
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fpga_gmii
Update vivado.mk
2023-01-13 14:57:46 -08:00
fpga_rgmii
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2023-01-13 14:57:46 -08:00