FPGA/verilog-ethernet
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Alex Forencich 8214e2abf9 added axis as a subproject 
git-subtree-dir: lib/axis
git-subtree-mainline: d64445b9e057cf97ae8fd57fbe83c5505c6ba45c
git-subtree-split: ac2f7e546df3b7f4a936cdb4d558adc517c5ddb4
2014-11-05 17:25:00 -08:00
lib
added axis as a subproject
2014-11-05 17:25:00 -08:00
rtl
Remove AXI stream components
2014-11-05 16:59:59 -08:00
tb
Remove AXI stream components
2014-11-05 16:59:59 -08:00
.gitignore
Initial commit
2014-09-13 21:17:57 -07:00
AUTHORS
Initial commit
2014-09-13 21:17:57 -07:00
COPYING
Initial commit
2014-09-13 21:17:57 -07:00
README
Initial commit
2014-09-13 21:17:57 -07:00

README 

Verilog ethernet components
Description
No description provided
Readme 106 MiB
Languages
Verilog 46.2%
Python 32.5%
Tcl 13.9%
Makefile 7.3%