mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-28 07:03:08 +08:00
68 lines
2.5 KiB
Makefile
68 lines
2.5 KiB
Makefile
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# FPGA settings
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FPGA_PART = xc6vhx565t-2ff1923
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FPGA_TOP = fpga
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FPGA_ARCH = spartan6
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# PROM settings
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#PROM = xc18v04
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#SPI_PROM_SIZE = (in bytes)
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# Files for synthesis
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SYN_FILES = rtl/fpga.v
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SYN_FILES += rtl/fpga_core.v
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SYN_FILES += rtl/debounce_switch.v
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SYN_FILES += rtl/sync_signal.v
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SYN_FILES += rtl/i2c_master.v
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SYN_FILES += rtl/gth_i2c_init.v
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SYN_FILES += rtl/eth_gth_phy_quad.v
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SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
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SYN_FILES += lib/eth/rtl/eth_mac_10g.v
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SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
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SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
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SYN_FILES += lib/eth/rtl/lfsr.v
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SYN_FILES += lib/eth/rtl/eth_axis_rx_64.v
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SYN_FILES += lib/eth/rtl/eth_axis_tx_64.v
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SYN_FILES += lib/eth/lib/axis/rtl/axis_crosspoint.v
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SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
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SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
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SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
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SYN_FILES += coregen/ten_gig_eth_pcs_pma_v2_6/ten_gig_eth_pcs_pma_v2_6.v
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SYN_FILES += coregen/ten_gig_eth_pcs_pma_v2_6/ten_gig_eth_pcs_pma_v2_6/example_design/ten_gig_eth_pcs_pma_v2_6_management_arbiter.v
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SYN_FILES += coregen/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper_quad.v
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SYN_FILES += coregen/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper_gth_reset.v
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SYN_FILES += coregen/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper_gth_init.v
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SYN_FILES += coregen/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper_gth_tx_pcs_reset.v
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SYN_FILES += coregen/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper_gth_rx_pcs_cdr_reset.v
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SYN_FILES += coregen/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper_pulse_synchronizer.v
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# UCF files
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UCF_FILES = fpga.ucf
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# NGC paths for ngdbuild
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NGC_PATHS = coregen/ten_gig_eth_pcs_pma_v2_6
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# Bitgen options
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BITGEN_OPTIONS = -g StartupClk:Cclk -g ConfigRate:26
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include ../common/xilinx.mk
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program: $(FPGA_TOP).bit
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echo "setmode -bscan" > program.cmd
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echo "setcable -p auto" >> program.cmd
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echo "identify" >> program.cmd
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echo "assignfile -p 1 -file $(FPGA_TOP).bit" >> program.cmd
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echo "program -p 1" >> program.cmd
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echo "quit" >> program.cmd
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impact -batch program.cmd
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program_flash: $(FPGA_TOP).mcs
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echo "setmode -bscan" > program.cmd
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echo "setcable -p auto" >> program.cmd
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echo "identify" >> program.cmd
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echo "assignfile -p 1 -file $(FPGA_TOP).mcs" >> program.cmd
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echo "program -p 1 -e" >> program.cmd
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echo "quit" >> program.cmd
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impact -batch program.cmd
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