mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-14 06:43:18 +08:00
108 lines
5.5 KiB
Tcl
108 lines
5.5 KiB
Tcl
# Copyright (c) 2019-2023 Alex Forencich
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
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# of this software and associated documentation files (the "Software"), to deal
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# in the Software without restriction, including without limitation the rights
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# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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# copies of the Software, and to permit persons to whom the Software is
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# furnished to do so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included in
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# all copies or substantial portions of the Software.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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# THE SOFTWARE.
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# PTP timestamp capture module
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foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == ptp_clock_cdc || REF_NAME == ptp_clock_cdc)}] {
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puts "Inserting timing constraints for ptp_clock_cdc instance $inst"
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# get clock periods
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set input_clk [get_clocks -of_objects [get_pins "$inst/src_sync_reg_reg/C"]]
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set output_clk [get_clocks -of_objects [get_pins "$inst/dest_sync_reg_reg/C"]]
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set input_clk_period [if {[llength $input_clk]} {get_property -min PERIOD $input_clk} {expr 1.0}]
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set output_clk_period [if {[llength $output_clk]} {get_property -min PERIOD $output_clk} {expr 1.0}]
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# timestamp synchronization
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set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/src_ts_(s|ns|step)_sync_reg_reg(\\\[\\d+\\\])?" -filter "PARENT == $inst"]
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if {[llength [get_cells "$inst/src_ts_s_capt_reg_reg[*]"]]} {
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set_max_delay -from [get_cells "$inst/src_ts_s_capt_reg_reg[*]"] -to [get_cells "$inst/src_ts_s_sync_reg_reg[*]"] -datapath_only $output_clk_period
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set_bus_skew -from [get_cells "$inst/src_ts_s_capt_reg_reg[*]"] -to [get_cells "$inst/src_ts_s_sync_reg_reg[*]"] $input_clk_period
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}
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set_max_delay -from [get_cells "$inst/src_ts_ns_capt_reg_reg[*]"] -to [get_cells "$inst/src_ts_ns_sync_reg_reg[*]"] -datapath_only $output_clk_period
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set_bus_skew -from [get_cells "$inst/src_ts_ns_capt_reg_reg[*]"] -to [get_cells "$inst/src_ts_ns_sync_reg_reg[*]"] $input_clk_period
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if {[llength [get_cells "$inst/src_ts_step_capt_reg_reg"]]} {
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set_max_delay -from [get_cells "$inst/src_ts_step_capt_reg_reg"] -to [get_cells "$inst/src_ts_step_sync_reg_reg"] -datapath_only $output_clk_period
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set_bus_skew -from [get_cells "$inst/src_ts_step_capt_reg_reg"] -to [get_cells "$inst/src_ts_step_sync_reg_reg"] $input_clk_period
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}
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# sample clock
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set sync_ffs [get_cells -quiet -hier -regexp ".*/src_sync_sample_sync\[12\]_reg_reg" -filter "PARENT == $inst"]
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if {[llength $sync_ffs]} {
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set_property ASYNC_REG TRUE $sync_ffs
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set_max_delay -from [get_cells "$inst/src_sync_reg_reg"] -to [get_cells "$inst/src_sync_sample_sync1_reg_reg"] -datapath_only $input_clk_period
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}
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set sync_ffs [get_cells -quiet -hier -regexp ".*/dest_sync_sample_sync\[12\]_reg_reg" -filter "PARENT == $inst"]
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if {[llength $sync_ffs]} {
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set_property ASYNC_REG TRUE $sync_ffs
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set_max_delay -from [get_cells "$inst/dest_sync_reg_reg"] -to [get_cells "$inst/dest_sync_sample_sync1_reg_reg"] -datapath_only $output_clk_period
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}
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# sample update sync
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set sync_ffs [get_cells -quiet -hier -regexp ".*/sample_update_sync\[123\]_reg_reg" -filter "PARENT == $inst"]
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if {[llength $sync_ffs]} {
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set_property ASYNC_REG TRUE $sync_ffs
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set src_clk [get_clocks -of_objects [get_pins "$inst/sample_update_reg_reg/C"]]
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set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 1.0}]
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set_max_delay -from [get_cells "$inst/sample_update_reg_reg"] -to [get_cells "$inst/sample_update_sync1_reg_reg"] -datapath_only $src_clk_period
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set_max_delay -from [get_cells "$inst/sample_acc_out_reg_reg[*]"] -to [get_cells $inst/sample_acc_sync_reg_reg[*]] -datapath_only $src_clk_period
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set_bus_skew -from [get_cells "$inst/sample_acc_out_reg_reg[*]"] -to [get_cells $inst/sample_acc_sync_reg_reg[*]] $output_clk_period
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}
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# timestamp transfer sync
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set sync_ffs [get_cells -quiet -hier -regexp ".*/src_sync_sync\[12\]_reg_reg" -filter "PARENT == $inst"]
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if {[llength $sync_ffs]} {
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set_property ASYNC_REG TRUE $sync_ffs
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set_max_delay -from [get_cells "$inst/src_sync_reg_reg"] -to [get_cells "$inst/src_sync_sync1_reg_reg"] -datapath_only $input_clk_period
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}
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# phase sync
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set sync_ffs [get_cells -quiet -hier -regexp ".*/src_phase_sync_sync\[12\]_reg_reg" -filter "PARENT == $inst"]
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if {[llength $sync_ffs]} {
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set_property ASYNC_REG TRUE $sync_ffs
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# hunt down source
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set dest_pins [get_pins -of_objects [get_cells "$inst/src_phase_sync_sync1_reg_reg"] -filter {REF_PIN_NAME == "D"}]
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set nets [get_nets -segments -of_objects $dest_pins]
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set source_pins [get_pins -of_objects $nets -filter {IS_LEAF && DIRECTION == "OUT"}]
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set source [get_cells -of_objects $source_pins]
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if {[llength $source]} {
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set_max_delay -from $source -to [get_cells "$inst/src_phase_sync_sync1_reg_reg"] -datapath_only $input_clk_period
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}
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}
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}
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