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34 lines
1.0 KiB
Markdown
34 lines
1.0 KiB
Markdown
# Verilog Ethernet Alveo Example Design
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## Introduction
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This design targets multiple FPGA boards, including most of the Xilinx Alveo line.
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The design by default listens to UDP port 1234 at IP address 192.168.1.128 and will echo back any packets received. The design will also respond correctly to ARP requests.
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* FPGA
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* AU50: xcu50-fsvh2104-2-e
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* AU55C: xcu55c-fsvh2892-2L-e
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* AU55N/C1100: xcu55n-fsvh2892-2L-e
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* AU200: xcu200-fsgd2104-2-e
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* AU250: xcu250-fsgd2104-2-e
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* AU280: xcu280-fsvh2892-2L-e
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* VCU1525: xcvu9p-fsgd2104-2L-e
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* PHY: 10G BASE-R PHY IP core and internal GTY transceiver
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## How to build
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Run make to build. Ensure that the Xilinx Vivado toolchain components are in PATH.
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## How to test
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Run make program to program the FPGA board with Vivado. Then run
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netcat -u 192.168.1.128 1234
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to open a UDP connection to port 1234. Any text entered into netcat will be echoed back after pressing enter.
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It is also possible to use hping to test the design by running
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hping 192.168.1.128 -2 -p 1234 -d 1024
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