mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-28 07:03:08 +08:00
270 lines
6.3 KiB
Verilog
270 lines
6.3 KiB
Verilog
/*
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Copyright (c) 2020 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* FPGA top-level module
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*/
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module fpga (
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/*
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* Clock: 125MHz
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*/
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input wire CLOCK_50,
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/*
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* GPIO
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*/
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input wire [3:0] KEY,
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input wire [17:0] SW,
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output wire [8:0] LEDG,
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output wire [17:0] LEDR,
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output wire [6:0] HEX0,
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output wire [6:0] HEX1,
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output wire [6:0] HEX2,
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output wire [6:0] HEX3,
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output wire [6:0] HEX4,
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output wire [6:0] HEX5,
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output wire [6:0] HEX6,
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output wire [6:0] HEX7,
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output wire [35:0] GPIO,
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/*
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* Ethernet: 1000BASE-T RGMII
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*/
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output wire ENET0_GTX_CLK,
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output wire [3:0] ENET0_TX_DATA,
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output wire ENET0_TX_EN,
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input wire ENET0_RX_CLK,
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input wire [3:0] ENET0_RX_DATA,
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input wire ENET0_RX_DV,
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output wire ENET0_RST_N,
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input wire ENET0_INT_N,
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output wire ENET1_GTX_CLK,
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output wire [3:0] ENET1_TX_DATA,
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output wire ENET1_TX_EN,
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input wire ENET1_RX_CLK,
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input wire [3:0] ENET1_RX_DATA,
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input wire ENET1_RX_DV,
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output wire ENET1_RST_N,
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input wire ENET1_INT_N
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);
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// Clock and reset
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// Internal 125 MHz clock
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wire clk_int;
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wire rst_int;
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wire pll_rst = ~KEY[3];
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wire pll_locked;
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wire clk90_int;
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altpll #(
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.bandwidth_type("AUTO"),
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.clk0_divide_by(2),
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.clk0_duty_cycle(50),
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.clk0_multiply_by(5),
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.clk0_phase_shift("0"),
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.clk1_divide_by(2),
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.clk1_duty_cycle(50),
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.clk1_multiply_by(5),
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.clk1_phase_shift("2000"),
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.compensate_clock("CLK0"),
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.inclk0_input_frequency(20000),
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.intended_device_family("Cyclone IV E"),
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.operation_mode("NORMAL"),
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.pll_type("AUTO"),
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.port_activeclock("PORT_UNUSED"),
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.port_areset("PORT_USED"),
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.port_clkbad0("PORT_UNUSED"),
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.port_clkbad1("PORT_UNUSED"),
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.port_clkloss("PORT_UNUSED"),
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.port_clkswitch("PORT_UNUSED"),
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.port_configupdate("PORT_UNUSED"),
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.port_fbin("PORT_UNUSED"),
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.port_inclk0("PORT_USED"),
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.port_inclk1("PORT_UNUSED"),
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.port_locked("PORT_USED"),
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.port_pfdena("PORT_UNUSED"),
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.port_phasecounterselect("PORT_UNUSED"),
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.port_phasedone("PORT_UNUSED"),
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.port_phasestep("PORT_UNUSED"),
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.port_phaseupdown("PORT_UNUSED"),
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.port_pllena("PORT_UNUSED"),
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.port_scanaclr("PORT_UNUSED"),
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.port_scanclk("PORT_UNUSED"),
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.port_scanclkena("PORT_UNUSED"),
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.port_scandata("PORT_UNUSED"),
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.port_scandataout("PORT_UNUSED"),
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.port_scandone("PORT_UNUSED"),
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.port_scanread("PORT_UNUSED"),
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.port_scanwrite("PORT_UNUSED"),
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.port_clk0("PORT_USED"),
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.port_clk1("PORT_USED"),
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.port_clk2("PORT_UNUSED"),
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.port_clk3("PORT_UNUSED"),
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.port_clk4("PORT_UNUSED"),
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.port_clk5("PORT_UNUSED"),
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.port_clkena0("PORT_UNUSED"),
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.port_clkena1("PORT_UNUSED"),
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.port_clkena2("PORT_UNUSED"),
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.port_clkena3("PORT_UNUSED"),
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.port_clkena4("PORT_UNUSED"),
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.port_clkena5("PORT_UNUSED"),
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.port_extclk0("PORT_UNUSED"),
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.port_extclk1("PORT_UNUSED"),
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.port_extclk2("PORT_UNUSED"),
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.port_extclk3("PORT_UNUSED"),
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.self_reset_on_loss_lock("ON"),
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.width_clock(5)
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)
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altpll_component (
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.areset(pll_rst),
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.inclk({1'b0, CLOCK_50}),
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.clk({clk90_int, clk_int}),
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.locked(pll_locked),
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.activeclock(),
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.clkbad(),
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.clkena({6{1'b1}}),
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.clkloss(),
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.clkswitch(1'b0),
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.configupdate(1'b0),
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.enable0(),
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.enable1(),
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.extclk(),
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.extclkena({4{1'b1}}),
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.fbin(1'b1),
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.fbmimicbidir(),
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.fbout(),
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.fref(),
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.icdrclk(),
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.pfdena(1'b1),
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.phasecounterselect({4{1'b1}}),
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.phasedone(),
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.phasestep(1'b1),
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.phaseupdown(1'b1),
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.pllena(1'b1),
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.scanaclr(1'b0),
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.scanclk(1'b0),
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.scanclkena(1'b1),
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.scandata(1'b0),
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.scandataout(),
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.scandone(),
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.scanread(1'b0),
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.scanwrite(1'b0),
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.sclkout0(),
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.sclkout1(),
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.vcooverrange(),
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.vcounderrange()
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);
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sync_reset #(
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.N(4)
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)
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sync_reset_inst (
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.clk(clk_int),
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.rst(~pll_locked),
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.out(rst_int)
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);
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// GPIO
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wire [3:0] btn_int;
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wire [17:0] sw_int;
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debounce_switch #(
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.WIDTH(4+18),
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.N(4),
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.RATE(125000)
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)
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debounce_switch_inst (
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.clk(clk_int),
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.rst(rst_int),
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.in({~KEY,
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SW}),
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.out({btn_int,
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sw_int})
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);
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fpga_core #(
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.TARGET("ALTERA")
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)
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core_inst (
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/*
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* Clock: 125MHz
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* Synchronous reset
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*/
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.clk(clk_int),
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.clk90(clk90_int),
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.rst(rst_int),
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/*
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* GPIO
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*/
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.btn(btn_int),
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.sw(sw_int),
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.ledg(LEDG),
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.ledr(LEDR),
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.hex0(HEX0),
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.hex1(HEX1),
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.hex2(HEX2),
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.hex3(HEX3),
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.hex4(HEX4),
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.hex5(HEX5),
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.hex6(HEX6),
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.hex7(HEX7),
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.gpio(GPIO),
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/*
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* Ethernet: 1000BASE-T RGMII
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*/
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.phy0_rx_clk(ENET0_RX_CLK),
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.phy0_rxd(ENET0_RX_DATA),
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.phy0_rx_ctl(ENET0_RX_DV),
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.phy0_tx_clk(ENET0_GTX_CLK),
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.phy0_txd(ENET0_TX_DATA),
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.phy0_tx_ctl(ENET0_TX_EN),
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.phy0_reset_n(ENET0_RST_N),
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.phy0_int_n(ENET0_INT_N),
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.phy1_rx_clk(ENET1_RX_CLK),
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.phy1_rxd(ENET1_RX_DATA),
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.phy1_rx_ctl(ENET1_RX_DV),
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.phy1_tx_clk(ENET1_GTX_CLK),
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.phy1_txd(ENET1_TX_DATA),
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.phy1_tx_ctl(ENET1_TX_EN),
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.phy1_reset_n(ENET1_RST_N),
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.phy1_int_n(ENET1_INT_N)
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);
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endmodule
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`resetall
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