verilog-ethernet/fpga at 92830f87d8b36d09ae1f065f703406084fd2c21e - verilog-ethernet - Gitea: Git with a cup of tea

FPGA/verilog-ethernet

mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-21 06:53:10 +08:00

History

Alex Forencich 92830f87d8 Update for Python 3

2015-04-01 19:43:54 -07:00

..

Add example design for Digilent Atlys board

2015-02-28 20:05:05 -08:00

Add example design for Digilent Atlys board

2015-02-28 20:05:05 -08:00

Add example design for Digilent Atlys board

2015-02-28 20:05:05 -08:00

Add example design for Digilent Atlys board

2015-02-28 20:05:05 -08:00

Add example design for Digilent Atlys board

2015-02-28 20:05:05 -08:00

Update for Python 3

2015-04-01 19:43:54 -07:00

clock.ucf

Add example design for Digilent Atlys board

2015-02-28 20:05:05 -08:00

fpga.ucf

Add example design for Digilent Atlys board

2015-02-28 20:05:05 -08:00

Makefile

Add example design for Digilent Atlys board

2015-02-28 20:05:05 -08:00