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21 lines
526 B
Plaintext
21 lines
526 B
Plaintext
# Date: Sat Jan 07 00:34:24 2012
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SET addpads = false
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SET asysymbol = true
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = false
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SET designentry = Verilog
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SET device = xc6slx45
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SET devicefamily = spartan6
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SET flowvendor = Foundation_ISE
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SET formalverification = false
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SET foundationsym = false
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SET implementationfiletype = Ngc
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SET package = csg324
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SET removerpms = false
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SET simulationfiles = Behavioral
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SET speedgrade = -2
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SET verilogsim = true
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SET vhdlsim = false
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SET workingdirectory = .\tmp\
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# CRC: 90246c5
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