mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-14 06:43:18 +08:00
427 lines
16 KiB
Verilog
427 lines
16 KiB
Verilog
/*
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Copyright (c) 2014-2017 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4-Stream ethernet frame transmitter (Ethernet frame in, AXI out, 64 bit datapath)
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*/
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module eth_axis_tx_64
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(
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input wire clk,
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input wire rst,
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/*
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* Ethernet frame input
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*/
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input wire input_eth_hdr_valid,
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output wire input_eth_hdr_ready,
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input wire [47:0] input_eth_dest_mac,
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input wire [47:0] input_eth_src_mac,
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input wire [15:0] input_eth_type,
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input wire [63:0] input_eth_payload_tdata,
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input wire [7:0] input_eth_payload_tkeep,
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input wire input_eth_payload_tvalid,
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output wire input_eth_payload_tready,
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input wire input_eth_payload_tlast,
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input wire input_eth_payload_tuser,
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/*
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* AXI output
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*/
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output wire [63:0] output_axis_tdata,
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output wire [7:0] output_axis_tkeep,
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output wire output_axis_tvalid,
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input wire output_axis_tready,
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output wire output_axis_tlast,
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output wire output_axis_tuser,
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/*
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* Status signals
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*/
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output wire busy
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);
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/*
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Ethernet frame
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Field Length
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Destination MAC address 6 octets
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Source MAC address 6 octets
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Ethertype 2 octets
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This module receives an Ethernet frame with header fields in parallel along
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with the payload in an AXI stream, combines the header with the payload, and
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transmits the complete Ethernet frame on the output AXI stream interface.
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*/
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localparam [2:0]
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STATE_IDLE = 3'd0,
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STATE_WRITE_HEADER = 3'd1,
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STATE_WRITE_HEADER_LAST = 3'd2,
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STATE_WRITE_PAYLOAD = 3'd3;
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reg [2:0] state_reg = STATE_IDLE, state_next;
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// datapath control signals
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reg store_eth_hdr;
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reg flush_save;
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reg transfer_in_save;
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reg [7:0] frame_ptr_reg = 8'd0, frame_ptr_next;
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reg [47:0] eth_dest_mac_reg = 48'd0;
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reg [47:0] eth_src_mac_reg = 48'd0;
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reg [15:0] eth_type_reg = 16'd0;
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reg input_eth_hdr_ready_reg = 1'b0, input_eth_hdr_ready_next;
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reg input_eth_payload_tready_reg = 1'b0, input_eth_payload_tready_next;
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reg busy_reg = 1'b0;
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reg [63:0] save_eth_payload_tdata_reg = 64'd0;
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reg [7:0] save_eth_payload_tkeep_reg = 8'd0;
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reg save_eth_payload_tlast_reg = 1'b0;
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reg save_eth_payload_tuser_reg = 1'b0;
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reg [63:0] shift_eth_payload_tdata;
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reg [7:0] shift_eth_payload_tkeep;
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reg shift_eth_payload_tvalid;
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reg shift_eth_payload_tlast;
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reg shift_eth_payload_tuser;
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reg shift_eth_payload_input_tready;
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reg shift_eth_payload_extra_cycle;
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// internal datapath
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reg [63:0] output_axis_tdata_int;
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reg [7:0] output_axis_tkeep_int;
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reg output_axis_tvalid_int;
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reg output_axis_tready_int_reg = 1'b0;
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reg output_axis_tlast_int;
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reg output_axis_tuser_int;
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wire output_axis_tready_int_early;
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assign input_eth_hdr_ready = input_eth_hdr_ready_reg;
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assign input_eth_payload_tready = input_eth_payload_tready_reg;
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assign busy = busy_reg;
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always @* begin
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shift_eth_payload_tdata[47:0] = save_eth_payload_tdata_reg[63:16];
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shift_eth_payload_tkeep[5:0] = save_eth_payload_tkeep_reg[7:2];
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shift_eth_payload_extra_cycle = save_eth_payload_tlast_reg & (save_eth_payload_tkeep_reg[7:2] != 0);
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if (shift_eth_payload_extra_cycle) begin
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shift_eth_payload_tdata[63:48] = 16'd0;
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shift_eth_payload_tkeep[7:6] = 2'd0;
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shift_eth_payload_tvalid = 1'b1;
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shift_eth_payload_tlast = save_eth_payload_tlast_reg;
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shift_eth_payload_tuser = save_eth_payload_tuser_reg;
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shift_eth_payload_input_tready = flush_save;
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end else begin
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shift_eth_payload_tdata[63:48] = input_eth_payload_tdata[15:0];
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shift_eth_payload_tkeep[7:6] = input_eth_payload_tkeep[1:0];
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shift_eth_payload_tvalid = input_eth_payload_tvalid;
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shift_eth_payload_tlast = (input_eth_payload_tlast & (input_eth_payload_tkeep[7:2] == 0));
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shift_eth_payload_tuser = (input_eth_payload_tuser & (input_eth_payload_tkeep[7:2] == 0));
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shift_eth_payload_input_tready = ~(input_eth_payload_tlast & input_eth_payload_tvalid & transfer_in_save);
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end
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end
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always @* begin
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state_next = STATE_IDLE;
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input_eth_hdr_ready_next = 1'b0;
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input_eth_payload_tready_next = 1'b0;
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store_eth_hdr = 1'b0;
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flush_save = 1'b0;
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transfer_in_save = 1'b0;
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frame_ptr_next = frame_ptr_reg;
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output_axis_tdata_int = 64'd0;
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output_axis_tkeep_int = 8'd0;
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output_axis_tvalid_int = 1'b0;
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output_axis_tlast_int = 1'b0;
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output_axis_tuser_int = 1'b0;
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case (state_reg)
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STATE_IDLE: begin
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// idle state - wait for data
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frame_ptr_next = 8'd0;
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flush_save = 1'b1;
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input_eth_hdr_ready_next = 1'b1;
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if (input_eth_hdr_ready & input_eth_hdr_valid) begin
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store_eth_hdr = 1'b1;
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input_eth_hdr_ready_next = 1'b0;
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state_next = STATE_WRITE_HEADER;
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if (output_axis_tready_int_reg) begin
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output_axis_tvalid_int = 1'b1;
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output_axis_tdata_int[ 7: 0] = input_eth_dest_mac[47:40];
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output_axis_tdata_int[15: 8] = input_eth_dest_mac[39:32];
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output_axis_tdata_int[23:16] = input_eth_dest_mac[31:24];
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output_axis_tdata_int[31:24] = input_eth_dest_mac[23:16];
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output_axis_tdata_int[39:32] = input_eth_dest_mac[15: 8];
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output_axis_tdata_int[47:40] = input_eth_dest_mac[ 7: 0];
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output_axis_tdata_int[55:48] = input_eth_src_mac[47:40];
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output_axis_tdata_int[63:56] = input_eth_src_mac[39:32];
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output_axis_tkeep_int = 8'hff;
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frame_ptr_next = 8'd8;
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input_eth_payload_tready_next = output_axis_tready_int_early;
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state_next = STATE_WRITE_HEADER_LAST;
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end
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end else begin
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state_next = STATE_IDLE;
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end
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end
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STATE_WRITE_HEADER: begin
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// write header
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if (output_axis_tready_int_reg) begin
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frame_ptr_next = frame_ptr_reg + 8'd8;
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output_axis_tvalid_int = 1'b1;
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state_next = STATE_WRITE_HEADER;
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case (frame_ptr_reg)
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5'd00: begin
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output_axis_tdata_int[ 7: 0] = input_eth_dest_mac[47:40];
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output_axis_tdata_int[15: 8] = input_eth_dest_mac[39:32];
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output_axis_tdata_int[23:16] = input_eth_dest_mac[31:24];
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output_axis_tdata_int[31:24] = input_eth_dest_mac[23:16];
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output_axis_tdata_int[39:32] = input_eth_dest_mac[15: 8];
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output_axis_tdata_int[47:40] = input_eth_dest_mac[ 7: 0];
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output_axis_tdata_int[55:48] = input_eth_src_mac[47:40];
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output_axis_tdata_int[63:56] = input_eth_src_mac[39:32];
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output_axis_tkeep_int = 8'hff;
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input_eth_payload_tready_next = output_axis_tready_int_early & shift_eth_payload_input_tready;
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state_next = STATE_WRITE_HEADER_LAST;
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end
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endcase
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end else begin
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state_next = STATE_WRITE_HEADER;
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end
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end
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STATE_WRITE_HEADER_LAST: begin
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// last header word requires first payload word; process accordingly
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input_eth_payload_tready_next = output_axis_tready_int_early & shift_eth_payload_input_tready;
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if (input_eth_payload_tready & shift_eth_payload_tvalid) begin
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frame_ptr_next = frame_ptr_reg + 8'd8;
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output_axis_tvalid_int = 1'b1;
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transfer_in_save = 1'b1;
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output_axis_tdata_int[ 7: 0] = eth_src_mac_reg[31:24];
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output_axis_tdata_int[15: 8] = eth_src_mac_reg[23:16];
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output_axis_tdata_int[23:16] = eth_src_mac_reg[15: 8];
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output_axis_tdata_int[31:24] = eth_src_mac_reg[ 7: 0];
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output_axis_tdata_int[39:32] = eth_type_reg[15: 8];
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output_axis_tdata_int[47:40] = eth_type_reg[ 7: 0];
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output_axis_tdata_int[55:48] = shift_eth_payload_tdata[55:48];
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output_axis_tdata_int[63:56] = shift_eth_payload_tdata[63:56];
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output_axis_tkeep_int = {shift_eth_payload_tkeep[7:6], 6'h3F};
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output_axis_tlast_int = shift_eth_payload_tlast;
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output_axis_tuser_int = shift_eth_payload_tuser;
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if (shift_eth_payload_tlast) begin
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input_eth_payload_tready_next = 1'b0;
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flush_save = 1'b1;
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input_eth_hdr_ready_next = 1'b1;
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state_next = STATE_IDLE;
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end else begin
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state_next = STATE_WRITE_PAYLOAD;
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end
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end else begin
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state_next = STATE_WRITE_HEADER_LAST;
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end
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end
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STATE_WRITE_PAYLOAD: begin
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// write payload
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input_eth_payload_tready_next = output_axis_tready_int_early & shift_eth_payload_input_tready;
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output_axis_tdata_int = shift_eth_payload_tdata;
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output_axis_tkeep_int = shift_eth_payload_tkeep;
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output_axis_tvalid_int = shift_eth_payload_tvalid;
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output_axis_tlast_int = shift_eth_payload_tlast;
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output_axis_tuser_int = shift_eth_payload_tuser;
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if (output_axis_tready_int_reg & shift_eth_payload_tvalid) begin
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// word transfer through
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transfer_in_save = 1'b1;
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if (shift_eth_payload_tlast) begin
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input_eth_payload_tready_next = 1'b0;
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flush_save = 1'b1;
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input_eth_hdr_ready_next = 1'b1;
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state_next = STATE_IDLE;
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end else begin
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state_next = STATE_WRITE_PAYLOAD;
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end
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end else begin
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state_next = STATE_WRITE_PAYLOAD;
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end
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end
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endcase
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end
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always @(posedge clk) begin
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if (rst) begin
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state_reg <= STATE_IDLE;
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frame_ptr_reg <= 8'd0;
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input_eth_hdr_ready_reg <= 1'b0;
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input_eth_payload_tready_reg <= 1'b0;
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save_eth_payload_tlast_reg <= 1'b0;
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busy_reg <= 1'b0;
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end else begin
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state_reg <= state_next;
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frame_ptr_reg <= frame_ptr_next;
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input_eth_hdr_ready_reg <= input_eth_hdr_ready_next;
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input_eth_payload_tready_reg <= input_eth_payload_tready_next;
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busy_reg <= state_next != STATE_IDLE;
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// datapath
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if (store_eth_hdr) begin
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eth_dest_mac_reg <= input_eth_dest_mac;
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eth_src_mac_reg <= input_eth_src_mac;
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eth_type_reg <= input_eth_type;
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end
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if (flush_save) begin
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save_eth_payload_tlast_reg <= 1'b0;
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end else if (transfer_in_save) begin
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save_eth_payload_tlast_reg <= input_eth_payload_tlast;
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end
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end
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// datapath
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if (store_eth_hdr) begin
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eth_dest_mac_reg <= input_eth_dest_mac;
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eth_src_mac_reg <= input_eth_src_mac;
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eth_type_reg <= input_eth_type;
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end
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if (transfer_in_save) begin
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save_eth_payload_tdata_reg <= input_eth_payload_tdata;
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save_eth_payload_tkeep_reg <= input_eth_payload_tkeep;
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save_eth_payload_tuser_reg <= input_eth_payload_tuser;
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end
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end
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// output datapath logic
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reg [63:0] output_axis_tdata_reg = 64'd0;
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reg [7:0] output_axis_tkeep_reg = 8'd0;
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reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
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reg output_axis_tlast_reg = 1'b0;
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reg output_axis_tuser_reg = 1'b0;
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reg [63:0] temp_axis_tdata_reg = 64'd0;
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reg [7:0] temp_axis_tkeep_reg = 8'd0;
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reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next;
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reg temp_axis_tlast_reg = 1'b0;
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reg temp_axis_tuser_reg = 1'b0;
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// datapath control
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reg store_axis_int_to_output;
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reg store_axis_int_to_temp;
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reg store_axis_temp_to_output;
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assign output_axis_tdata = output_axis_tdata_reg;
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assign output_axis_tkeep = output_axis_tkeep_reg;
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assign output_axis_tvalid = output_axis_tvalid_reg;
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assign output_axis_tlast = output_axis_tlast_reg;
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assign output_axis_tuser = output_axis_tuser_reg;
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// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & (~output_axis_tvalid_reg | ~output_axis_tvalid_int));
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always @* begin
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// transfer sink ready state to source
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output_axis_tvalid_next = output_axis_tvalid_reg;
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temp_axis_tvalid_next = temp_axis_tvalid_reg;
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store_axis_int_to_output = 1'b0;
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store_axis_int_to_temp = 1'b0;
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store_axis_temp_to_output = 1'b0;
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if (output_axis_tready_int_reg) begin
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// input is ready
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if (output_axis_tready | ~output_axis_tvalid_reg) begin
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// output is ready or currently not valid, transfer data to output
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output_axis_tvalid_next = output_axis_tvalid_int;
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store_axis_int_to_output = 1'b1;
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end else begin
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// output is not ready, store input in temp
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temp_axis_tvalid_next = output_axis_tvalid_int;
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store_axis_int_to_temp = 1'b1;
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end
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end else if (output_axis_tready) begin
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// input is not ready, but output is ready
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output_axis_tvalid_next = temp_axis_tvalid_reg;
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temp_axis_tvalid_next = 1'b0;
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store_axis_temp_to_output = 1'b1;
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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output_axis_tvalid_reg <= 1'b0;
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output_axis_tready_int_reg <= 1'b0;
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temp_axis_tvalid_reg <= 1'b0;
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end else begin
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output_axis_tvalid_reg <= output_axis_tvalid_next;
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output_axis_tready_int_reg <= output_axis_tready_int_early;
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temp_axis_tvalid_reg <= temp_axis_tvalid_next;
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end
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// datapath
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if (store_axis_int_to_output) begin
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output_axis_tdata_reg <= output_axis_tdata_int;
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output_axis_tkeep_reg <= output_axis_tkeep_int;
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output_axis_tlast_reg <= output_axis_tlast_int;
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output_axis_tuser_reg <= output_axis_tuser_int;
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end else if (store_axis_temp_to_output) begin
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output_axis_tdata_reg <= temp_axis_tdata_reg;
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output_axis_tkeep_reg <= temp_axis_tkeep_reg;
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output_axis_tlast_reg <= temp_axis_tlast_reg;
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output_axis_tuser_reg <= temp_axis_tuser_reg;
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end
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if (store_axis_int_to_temp) begin
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temp_axis_tdata_reg <= output_axis_tdata_int;
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temp_axis_tkeep_reg <= output_axis_tkeep_int;
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temp_axis_tlast_reg <= output_axis_tlast_int;
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temp_axis_tuser_reg <= output_axis_tuser_int;
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end
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end
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endmodule
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