mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-14 06:43:18 +08:00
505 lines
19 KiB
Python
Executable File
505 lines
19 KiB
Python
Executable File
#!/usr/bin/env python
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"""
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Generates an IP mux with the specified number of ports
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"""
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from __future__ import print_function
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import argparse
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import math
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from jinja2 import Template
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def main():
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parser = argparse.ArgumentParser(description=__doc__.strip())
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parser.add_argument('-p', '--ports', type=int, default=4, help="number of ports")
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parser.add_argument('-n', '--name', type=str, help="module name")
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parser.add_argument('-o', '--output', type=str, help="output file name")
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args = parser.parse_args()
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try:
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generate(**args.__dict__)
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except IOError as ex:
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print(ex)
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exit(1)
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def generate(ports=4, name=None, output=None):
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if name is None:
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name = "ip_mux_{0}".format(ports)
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if output is None:
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output = name + ".v"
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print("Opening file '{0}'...".format(output))
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output_file = open(output, 'w')
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print("Generating {0} port IP mux {1}...".format(ports, name))
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select_width = int(math.ceil(math.log(ports, 2)))
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t = Template(u"""/*
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Copyright (c) 2014-2017 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* IP {{n}} port multiplexer
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*/
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module {{name}}
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(
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input wire clk,
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input wire rst,
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/*
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* IP frame inputs
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*/
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{%- for p in ports %}
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input wire input_{{p}}_ip_hdr_valid,
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output wire input_{{p}}_ip_hdr_ready,
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input wire [47:0] input_{{p}}_eth_dest_mac,
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input wire [47:0] input_{{p}}_eth_src_mac,
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input wire [15:0] input_{{p}}_eth_type,
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input wire [3:0] input_{{p}}_ip_version,
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input wire [3:0] input_{{p}}_ip_ihl,
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input wire [5:0] input_{{p}}_ip_dscp,
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input wire [1:0] input_{{p}}_ip_ecn,
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input wire [15:0] input_{{p}}_ip_length,
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input wire [15:0] input_{{p}}_ip_identification,
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input wire [2:0] input_{{p}}_ip_flags,
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input wire [12:0] input_{{p}}_ip_fragment_offset,
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input wire [7:0] input_{{p}}_ip_ttl,
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input wire [7:0] input_{{p}}_ip_protocol,
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input wire [15:0] input_{{p}}_ip_header_checksum,
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input wire [31:0] input_{{p}}_ip_source_ip,
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input wire [31:0] input_{{p}}_ip_dest_ip,
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input wire [7:0] input_{{p}}_ip_payload_tdata,
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input wire input_{{p}}_ip_payload_tvalid,
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output wire input_{{p}}_ip_payload_tready,
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input wire input_{{p}}_ip_payload_tlast,
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input wire input_{{p}}_ip_payload_tuser,
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{% endfor %}
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/*
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* IP frame output
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*/
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output wire output_ip_hdr_valid,
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input wire output_ip_hdr_ready,
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output wire [47:0] output_eth_dest_mac,
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output wire [47:0] output_eth_src_mac,
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output wire [15:0] output_eth_type,
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output wire [3:0] output_ip_version,
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output wire [3:0] output_ip_ihl,
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output wire [5:0] output_ip_dscp,
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output wire [1:0] output_ip_ecn,
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output wire [15:0] output_ip_length,
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output wire [15:0] output_ip_identification,
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output wire [2:0] output_ip_flags,
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output wire [12:0] output_ip_fragment_offset,
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output wire [7:0] output_ip_ttl,
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output wire [7:0] output_ip_protocol,
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output wire [15:0] output_ip_header_checksum,
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output wire [31:0] output_ip_source_ip,
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output wire [31:0] output_ip_dest_ip,
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output wire [7:0] output_ip_payload_tdata,
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output wire output_ip_payload_tvalid,
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input wire output_ip_payload_tready,
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output wire output_ip_payload_tlast,
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output wire output_ip_payload_tuser,
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/*
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* Control
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*/
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input wire enable,
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input wire [{{w-1}}:0] select
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);
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reg [{{w-1}}:0] select_reg = {{w}}'d0, select_next;
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reg frame_reg = 1'b0, frame_next;
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{% for p in ports %}
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reg input_{{p}}_ip_hdr_ready_reg = 1'b0, input_{{p}}_ip_hdr_ready_next;
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{%- endfor %}
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{% for p in ports %}
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reg input_{{p}}_ip_payload_tready_reg = 1'b0, input_{{p}}_ip_payload_tready_next;
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{%- endfor %}
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reg output_ip_hdr_valid_reg = 1'b0, output_ip_hdr_valid_next;
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reg [47:0] output_eth_dest_mac_reg = 48'd0, output_eth_dest_mac_next;
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reg [47:0] output_eth_src_mac_reg = 48'd0, output_eth_src_mac_next;
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reg [15:0] output_eth_type_reg = 16'd0, output_eth_type_next;
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reg [3:0] output_ip_version_reg = 4'd0, output_ip_version_next;
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reg [3:0] output_ip_ihl_reg = 4'd0, output_ip_ihl_next;
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reg [5:0] output_ip_dscp_reg = 6'd0, output_ip_dscp_next;
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reg [1:0] output_ip_ecn_reg = 2'd0, output_ip_ecn_next;
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reg [15:0] output_ip_length_reg = 16'd0, output_ip_length_next;
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reg [15:0] output_ip_identification_reg = 16'd0, output_ip_identification_next;
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reg [2:0] output_ip_flags_reg = 3'd0, output_ip_flags_next;
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reg [12:0] output_ip_fragment_offset_reg = 13'd0, output_ip_fragment_offset_next;
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reg [7:0] output_ip_ttl_reg = 8'd0, output_ip_ttl_next;
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reg [7:0] output_ip_protocol_reg = 8'd0, output_ip_protocol_next;
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reg [15:0] output_ip_header_checksum_reg = 16'd0, output_ip_header_checksum_next;
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reg [31:0] output_ip_source_ip_reg = 32'd0, output_ip_source_ip_next;
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reg [31:0] output_ip_dest_ip_reg = 32'd0, output_ip_dest_ip_next;
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// internal datapath
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reg [7:0] output_ip_payload_tdata_int;
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reg output_ip_payload_tvalid_int;
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reg output_ip_payload_tready_int_reg = 1'b0;
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reg output_ip_payload_tlast_int;
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reg output_ip_payload_tuser_int;
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wire output_ip_payload_tready_int_early;
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{% for p in ports %}
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assign input_{{p}}_ip_hdr_ready = input_{{p}}_ip_hdr_ready_reg;
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{%- endfor %}
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{% for p in ports %}
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assign input_{{p}}_ip_payload_tready = input_{{p}}_ip_payload_tready_reg;
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{%- endfor %}
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assign output_ip_hdr_valid = output_ip_hdr_valid_reg;
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assign output_eth_dest_mac = output_eth_dest_mac_reg;
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assign output_eth_src_mac = output_eth_src_mac_reg;
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assign output_eth_type = output_eth_type_reg;
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assign output_ip_version = output_ip_version_reg;
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assign output_ip_ihl = output_ip_ihl_reg;
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assign output_ip_dscp = output_ip_dscp_reg;
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assign output_ip_ecn = output_ip_ecn_reg;
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assign output_ip_length = output_ip_length_reg;
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assign output_ip_identification = output_ip_identification_reg;
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assign output_ip_flags = output_ip_flags_reg;
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assign output_ip_fragment_offset = output_ip_fragment_offset_reg;
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assign output_ip_ttl = output_ip_ttl_reg;
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assign output_ip_protocol = output_ip_protocol_reg;
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assign output_ip_header_checksum = output_ip_header_checksum_reg;
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assign output_ip_source_ip = output_ip_source_ip_reg;
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assign output_ip_dest_ip = output_ip_dest_ip_reg;
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// mux for start of packet detection
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reg selected_input_ip_hdr_valid;
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reg [47:0] selected_input_eth_dest_mac;
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reg [47:0] selected_input_eth_src_mac;
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reg [15:0] selected_input_eth_type;
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reg [3:0] selected_input_ip_version;
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reg [3:0] selected_input_ip_ihl;
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reg [5:0] selected_input_ip_dscp;
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reg [1:0] selected_input_ip_ecn;
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reg [15:0] selected_input_ip_length;
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reg [15:0] selected_input_ip_identification;
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reg [2:0] selected_input_ip_flags;
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reg [12:0] selected_input_ip_fragment_offset;
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reg [7:0] selected_input_ip_ttl;
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reg [7:0] selected_input_ip_protocol;
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reg [15:0] selected_input_ip_header_checksum;
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reg [31:0] selected_input_ip_source_ip;
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reg [31:0] selected_input_ip_dest_ip;
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always @* begin
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case (select)
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{%- for p in ports %}
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{{w}}'d{{p}}: begin
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selected_input_ip_hdr_valid = input_{{p}}_ip_hdr_valid;
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selected_input_eth_dest_mac = input_{{p}}_eth_dest_mac;
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selected_input_eth_src_mac = input_{{p}}_eth_src_mac;
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selected_input_eth_type = input_{{p}}_eth_type;
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selected_input_ip_version = input_{{p}}_ip_version;
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selected_input_ip_ihl = input_{{p}}_ip_ihl;
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selected_input_ip_dscp = input_{{p}}_ip_dscp;
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selected_input_ip_ecn = input_{{p}}_ip_ecn;
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selected_input_ip_length = input_{{p}}_ip_length;
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selected_input_ip_identification = input_{{p}}_ip_identification;
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selected_input_ip_flags = input_{{p}}_ip_flags;
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selected_input_ip_fragment_offset = input_{{p}}_ip_fragment_offset;
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selected_input_ip_ttl = input_{{p}}_ip_ttl;
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selected_input_ip_protocol = input_{{p}}_ip_protocol;
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selected_input_ip_header_checksum = input_{{p}}_ip_header_checksum;
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selected_input_ip_source_ip = input_{{p}}_ip_source_ip;
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selected_input_ip_dest_ip = input_{{p}}_ip_dest_ip;
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end
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{%- endfor %}
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default: begin
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selected_input_ip_hdr_valid = 1'b0;
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selected_input_eth_dest_mac = 48'd0;
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selected_input_eth_src_mac = 48'd0;
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selected_input_eth_type = 16'd0;
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selected_input_ip_version = 4'd0;
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selected_input_ip_ihl = 4'd0;
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selected_input_ip_dscp = 6'd0;
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selected_input_ip_ecn = 2'd0;
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selected_input_ip_length = 16'd0;
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selected_input_ip_identification = 16'd0;
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selected_input_ip_flags = 3'd0;
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selected_input_ip_fragment_offset = 13'd0;
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selected_input_ip_ttl = 8'd0;
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selected_input_ip_protocol = 8'd0;
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selected_input_ip_header_checksum = 16'd0;
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selected_input_ip_source_ip = 32'd0;
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selected_input_ip_dest_ip = 32'd0;
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end
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endcase
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end
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// mux for incoming packet
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reg [7:0] current_input_tdata;
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reg current_input_tvalid;
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reg current_input_tready;
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reg current_input_tlast;
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reg current_input_tuser;
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always @* begin
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case (select_reg)
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{%- for p in ports %}
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{{w}}'d{{p}}: begin
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current_input_tdata = input_{{p}}_ip_payload_tdata;
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current_input_tvalid = input_{{p}}_ip_payload_tvalid;
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current_input_tready = input_{{p}}_ip_payload_tready;
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current_input_tlast = input_{{p}}_ip_payload_tlast;
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current_input_tuser = input_{{p}}_ip_payload_tuser;
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end
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{%- endfor %}
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default: begin
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current_input_tdata = 8'd0;
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current_input_tvalid = 1'b0;
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current_input_tready = 1'b0;
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current_input_tlast = 1'b0;
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current_input_tuser = 1'b0;
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end
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endcase
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end
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always @* begin
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select_next = select_reg;
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frame_next = frame_reg;
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{% for p in ports %}
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input_{{p}}_ip_hdr_ready_next = input_{{p}}_ip_hdr_ready_reg & ~input_{{p}}_ip_hdr_valid;
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{%- endfor %}
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{% for p in ports %}
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input_{{p}}_ip_payload_tready_next = 1'b0;
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{%- endfor %}
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output_ip_hdr_valid_next = output_ip_hdr_valid_reg & ~output_ip_hdr_ready;
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output_eth_dest_mac_next = output_eth_dest_mac_reg;
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output_eth_src_mac_next = output_eth_src_mac_reg;
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output_eth_type_next = output_eth_type_reg;
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output_ip_version_next = output_ip_version_reg;
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output_ip_ihl_next = output_ip_ihl_reg;
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output_ip_dscp_next = output_ip_dscp_reg;
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output_ip_ecn_next = output_ip_ecn_reg;
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output_ip_length_next = output_ip_length_reg;
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output_ip_identification_next = output_ip_identification_reg;
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output_ip_flags_next = output_ip_flags_reg;
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output_ip_fragment_offset_next = output_ip_fragment_offset_reg;
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output_ip_ttl_next = output_ip_ttl_reg;
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output_ip_protocol_next = output_ip_protocol_reg;
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output_ip_header_checksum_next = output_ip_header_checksum_reg;
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output_ip_source_ip_next = output_ip_source_ip_reg;
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output_ip_dest_ip_next = output_ip_dest_ip_reg;
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if (current_input_tvalid & current_input_tready) begin
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// end of frame detection
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if (current_input_tlast) begin
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frame_next = 1'b0;
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end
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end
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if (~frame_reg & enable & ~output_ip_hdr_valid & selected_input_ip_hdr_valid) begin
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// start of frame, grab select value
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frame_next = 1'b1;
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select_next = select;
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case (select_next)
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{%- for p in ports %}
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{{w}}'d{{p}}: input_{{p}}_ip_hdr_ready_next = 1'b1;
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{%- endfor %}
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endcase
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output_ip_hdr_valid_next = 1;
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output_eth_dest_mac_next = selected_input_eth_dest_mac;
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output_eth_src_mac_next = selected_input_eth_src_mac;
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output_eth_type_next = selected_input_eth_type;
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output_ip_version_next = selected_input_ip_version;
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output_ip_ihl_next = selected_input_ip_ihl;
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output_ip_dscp_next = selected_input_ip_dscp;
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output_ip_ecn_next = selected_input_ip_ecn;
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output_ip_length_next = selected_input_ip_length;
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output_ip_identification_next = selected_input_ip_identification;
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output_ip_flags_next = selected_input_ip_flags;
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output_ip_fragment_offset_next = selected_input_ip_fragment_offset;
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output_ip_ttl_next = selected_input_ip_ttl;
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output_ip_protocol_next = selected_input_ip_protocol;
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output_ip_header_checksum_next = selected_input_ip_header_checksum;
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output_ip_source_ip_next = selected_input_ip_source_ip;
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output_ip_dest_ip_next = selected_input_ip_dest_ip;
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end
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// generate ready signal on selected port
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case (select_next)
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{%- for p in ports %}
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{{w}}'d{{p}}: input_{{p}}_ip_payload_tready_next = output_ip_payload_tready_int_early & frame_next;
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{%- endfor %}
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endcase
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// pass through selected packet data
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output_ip_payload_tdata_int = current_input_tdata;
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output_ip_payload_tvalid_int = current_input_tvalid & current_input_tready & frame_reg;
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output_ip_payload_tlast_int = current_input_tlast;
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output_ip_payload_tuser_int = current_input_tuser;
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end
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always @(posedge clk) begin
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if (rst) begin
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select_reg <= {{w}}'d0;
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frame_reg <= 1'b0;
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{%- for p in ports %}
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input_{{p}}_ip_hdr_ready_reg <= 1'b0;
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{%- endfor %}
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{%- for p in ports %}
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input_{{p}}_ip_payload_tready_reg <= 1'b0;
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{%- endfor %}
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output_ip_hdr_valid_reg <= 1'b0;
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end else begin
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select_reg <= select_next;
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frame_reg <= frame_next;
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{%- for p in ports %}
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input_{{p}}_ip_hdr_ready_reg <= input_{{p}}_ip_hdr_ready_next;
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{%- endfor %}
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{%- for p in ports %}
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input_{{p}}_ip_payload_tready_reg <= input_{{p}}_ip_payload_tready_next;
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{%- endfor %}
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output_ip_hdr_valid_reg <= output_ip_hdr_valid_next;
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end
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output_eth_dest_mac_reg <= output_eth_dest_mac_next;
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output_eth_src_mac_reg <= output_eth_src_mac_next;
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output_eth_type_reg <= output_eth_type_next;
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output_ip_version_reg <= output_ip_version_next;
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output_ip_ihl_reg <= output_ip_ihl_next;
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output_ip_dscp_reg <= output_ip_dscp_next;
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output_ip_ecn_reg <= output_ip_ecn_next;
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output_ip_length_reg <= output_ip_length_next;
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output_ip_identification_reg <= output_ip_identification_next;
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output_ip_flags_reg <= output_ip_flags_next;
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output_ip_fragment_offset_reg <= output_ip_fragment_offset_next;
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output_ip_ttl_reg <= output_ip_ttl_next;
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output_ip_protocol_reg <= output_ip_protocol_next;
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output_ip_header_checksum_reg <= output_ip_header_checksum_next;
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output_ip_source_ip_reg <= output_ip_source_ip_next;
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output_ip_dest_ip_reg <= output_ip_dest_ip_next;
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end
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// output datapath logic
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reg [7:0] output_ip_payload_tdata_reg = 8'd0;
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reg output_ip_payload_tvalid_reg = 1'b0, output_ip_payload_tvalid_next;
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reg output_ip_payload_tlast_reg = 1'b0;
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reg output_ip_payload_tuser_reg = 1'b0;
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|
|
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reg [7:0] temp_ip_payload_tdata_reg = 8'd0;
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reg temp_ip_payload_tvalid_reg = 1'b0, temp_ip_payload_tvalid_next;
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reg temp_ip_payload_tlast_reg = 1'b0;
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reg temp_ip_payload_tuser_reg = 1'b0;
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|
|
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// datapath control
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reg store_ip_payload_int_to_output;
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reg store_ip_payload_int_to_temp;
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reg store_ip_payload_temp_to_output;
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|
|
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assign output_ip_payload_tdata = output_ip_payload_tdata_reg;
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assign output_ip_payload_tvalid = output_ip_payload_tvalid_reg;
|
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assign output_ip_payload_tlast = output_ip_payload_tlast_reg;
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assign output_ip_payload_tuser = output_ip_payload_tuser_reg;
|
|
|
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// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
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assign output_ip_payload_tready_int_early = output_ip_payload_tready | (~temp_ip_payload_tvalid_reg & (~output_ip_payload_tvalid_reg | ~output_ip_payload_tvalid_int));
|
|
|
|
always @* begin
|
|
// transfer sink ready state to source
|
|
output_ip_payload_tvalid_next = output_ip_payload_tvalid_reg;
|
|
temp_ip_payload_tvalid_next = temp_ip_payload_tvalid_reg;
|
|
|
|
store_ip_payload_int_to_output = 1'b0;
|
|
store_ip_payload_int_to_temp = 1'b0;
|
|
store_ip_payload_temp_to_output = 1'b0;
|
|
|
|
if (output_ip_payload_tready_int_reg) begin
|
|
// input is ready
|
|
if (output_ip_payload_tready | ~output_ip_payload_tvalid_reg) begin
|
|
// output is ready or currently not valid, transfer data to output
|
|
output_ip_payload_tvalid_next = output_ip_payload_tvalid_int;
|
|
store_ip_payload_int_to_output = 1'b1;
|
|
end else begin
|
|
// output is not ready, store input in temp
|
|
temp_ip_payload_tvalid_next = output_ip_payload_tvalid_int;
|
|
store_ip_payload_int_to_temp = 1'b1;
|
|
end
|
|
end else if (output_ip_payload_tready) begin
|
|
// input is not ready, but output is ready
|
|
output_ip_payload_tvalid_next = temp_ip_payload_tvalid_reg;
|
|
temp_ip_payload_tvalid_next = 1'b0;
|
|
store_ip_payload_temp_to_output = 1'b1;
|
|
end
|
|
end
|
|
|
|
always @(posedge clk) begin
|
|
if (rst) begin
|
|
output_ip_payload_tvalid_reg <= 1'b0;
|
|
output_ip_payload_tready_int_reg <= 1'b0;
|
|
temp_ip_payload_tvalid_reg <= 1'b0;
|
|
end else begin
|
|
output_ip_payload_tvalid_reg <= output_ip_payload_tvalid_next;
|
|
output_ip_payload_tready_int_reg <= output_ip_payload_tready_int_early;
|
|
temp_ip_payload_tvalid_reg <= temp_ip_payload_tvalid_next;
|
|
end
|
|
|
|
// datapath
|
|
if (store_ip_payload_int_to_output) begin
|
|
output_ip_payload_tdata_reg <= output_ip_payload_tdata_int;
|
|
output_ip_payload_tlast_reg <= output_ip_payload_tlast_int;
|
|
output_ip_payload_tuser_reg <= output_ip_payload_tuser_int;
|
|
end else if (store_ip_payload_temp_to_output) begin
|
|
output_ip_payload_tdata_reg <= temp_ip_payload_tdata_reg;
|
|
output_ip_payload_tlast_reg <= temp_ip_payload_tlast_reg;
|
|
output_ip_payload_tuser_reg <= temp_ip_payload_tuser_reg;
|
|
end
|
|
|
|
if (store_ip_payload_int_to_temp) begin
|
|
temp_ip_payload_tdata_reg <= output_ip_payload_tdata_int;
|
|
temp_ip_payload_tlast_reg <= output_ip_payload_tlast_int;
|
|
temp_ip_payload_tuser_reg <= output_ip_payload_tuser_int;
|
|
end
|
|
end
|
|
|
|
endmodule
|
|
|
|
""")
|
|
|
|
output_file.write(t.render(
|
|
n=ports,
|
|
w=select_width,
|
|
name=name,
|
|
ports=range(ports)
|
|
))
|
|
|
|
print("Done")
|
|
|
|
if __name__ == "__main__":
|
|
main()
|
|
|