mirror of
https://github.com/alexforencich/verilog-ethernet.git
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529 lines
20 KiB
Verilog
529 lines
20 KiB
Verilog
/*
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Copyright (c) 2014-2017 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* UDP ethernet frame receiver (IP frame in, UDP frame out)
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*/
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module udp_ip_rx
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(
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input wire clk,
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input wire rst,
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/*
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* IP frame input
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*/
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input wire input_ip_hdr_valid,
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output wire input_ip_hdr_ready,
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input wire [47:0] input_eth_dest_mac,
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input wire [47:0] input_eth_src_mac,
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input wire [15:0] input_eth_type,
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input wire [3:0] input_ip_version,
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input wire [3:0] input_ip_ihl,
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input wire [5:0] input_ip_dscp,
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input wire [1:0] input_ip_ecn,
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input wire [15:0] input_ip_length,
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input wire [15:0] input_ip_identification,
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input wire [2:0] input_ip_flags,
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input wire [12:0] input_ip_fragment_offset,
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input wire [7:0] input_ip_ttl,
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input wire [7:0] input_ip_protocol,
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input wire [15:0] input_ip_header_checksum,
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input wire [31:0] input_ip_source_ip,
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input wire [31:0] input_ip_dest_ip,
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input wire [7:0] input_ip_payload_tdata,
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input wire input_ip_payload_tvalid,
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output wire input_ip_payload_tready,
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input wire input_ip_payload_tlast,
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input wire input_ip_payload_tuser,
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/*
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* UDP frame output
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*/
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output wire output_udp_hdr_valid,
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input wire output_udp_hdr_ready,
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output wire [47:0] output_eth_dest_mac,
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output wire [47:0] output_eth_src_mac,
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output wire [15:0] output_eth_type,
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output wire [3:0] output_ip_version,
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output wire [3:0] output_ip_ihl,
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output wire [5:0] output_ip_dscp,
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output wire [1:0] output_ip_ecn,
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output wire [15:0] output_ip_length,
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output wire [15:0] output_ip_identification,
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output wire [2:0] output_ip_flags,
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output wire [12:0] output_ip_fragment_offset,
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output wire [7:0] output_ip_ttl,
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output wire [7:0] output_ip_protocol,
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output wire [15:0] output_ip_header_checksum,
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output wire [31:0] output_ip_source_ip,
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output wire [31:0] output_ip_dest_ip,
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output wire [15:0] output_udp_source_port,
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output wire [15:0] output_udp_dest_port,
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output wire [15:0] output_udp_length,
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output wire [15:0] output_udp_checksum,
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output wire [7:0] output_udp_payload_tdata,
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output wire output_udp_payload_tvalid,
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input wire output_udp_payload_tready,
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output wire output_udp_payload_tlast,
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output wire output_udp_payload_tuser,
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/*
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* Status signals
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*/
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output wire busy,
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output wire error_header_early_termination,
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output wire error_payload_early_termination
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);
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/*
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UDP Frame
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Field Length
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Destination MAC address 6 octets
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Source MAC address 6 octets
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Ethertype (0x0800) 2 octets
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Version (4) 4 bits
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IHL (5-15) 4 bits
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DSCP (0) 6 bits
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ECN (0) 2 bits
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length 2 octets
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identification (0?) 2 octets
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flags (010) 3 bits
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fragment offset (0) 13 bits
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time to live (64?) 1 octet
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protocol 1 octet
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header checksum 2 octets
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source IP 4 octets
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destination IP 4 octets
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options (IHL-5)*4 octets
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source port 2 octets
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desination port 2 octets
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length 2 octets
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checksum 2 octets
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payload length octets
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This module receives an IP frame with header fields in parallel and payload on
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an AXI stream interface, decodes and strips the UDP header fields, then
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produces the header fields in parallel along with the UDP payload in a
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separate AXI stream.
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*/
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localparam [2:0]
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STATE_IDLE = 3'd0,
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STATE_READ_HEADER = 3'd1,
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STATE_READ_PAYLOAD = 3'd2,
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STATE_READ_PAYLOAD_LAST = 3'd3,
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STATE_WAIT_LAST = 3'd4;
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reg [2:0] state_reg = STATE_IDLE, state_next;
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// datapath control signals
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reg store_ip_hdr;
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reg store_udp_source_port_0;
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reg store_udp_source_port_1;
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reg store_udp_dest_port_0;
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reg store_udp_dest_port_1;
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reg store_udp_length_0;
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reg store_udp_length_1;
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reg store_udp_checksum_0;
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reg store_udp_checksum_1;
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reg store_last_word;
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reg [15:0] frame_ptr_reg = 16'd0, frame_ptr_next;
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reg [7:0] last_word_data_reg = 8'd0;
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reg output_udp_hdr_valid_reg = 1'b0, output_udp_hdr_valid_next;
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reg [47:0] output_eth_dest_mac_reg = 48'd0;
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reg [47:0] output_eth_src_mac_reg = 48'd0;
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reg [15:0] output_eth_type_reg = 16'd0;
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reg [3:0] output_ip_version_reg = 4'd0;
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reg [3:0] output_ip_ihl_reg = 4'd0;
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reg [5:0] output_ip_dscp_reg = 6'd0;
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reg [1:0] output_ip_ecn_reg = 2'd0;
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reg [15:0] output_ip_length_reg = 16'd0;
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reg [15:0] output_ip_identification_reg = 16'd0;
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reg [2:0] output_ip_flags_reg = 3'd0;
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reg [12:0] output_ip_fragment_offset_reg = 13'd0;
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reg [7:0] output_ip_ttl_reg = 8'd0;
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reg [7:0] output_ip_protocol_reg = 8'd0;
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reg [15:0] output_ip_header_checksum_reg = 16'd0;
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reg [31:0] output_ip_source_ip_reg = 32'd0;
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reg [31:0] output_ip_dest_ip_reg = 32'd0;
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reg [15:0] output_udp_source_port_reg = 16'd0;
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reg [15:0] output_udp_dest_port_reg = 16'd0;
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reg [15:0] output_udp_length_reg = 16'd0;
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reg [15:0] output_udp_checksum_reg = 16'd0;
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reg input_ip_hdr_ready_reg = 1'b0, input_ip_hdr_ready_next;
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reg input_ip_payload_tready_reg = 1'b0, input_ip_payload_tready_next;
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reg busy_reg = 1'b0;
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reg error_header_early_termination_reg = 1'b0, error_header_early_termination_next;
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reg error_payload_early_termination_reg = 1'b0, error_payload_early_termination_next;
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// internal datapath
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reg [7:0] output_udp_payload_tdata_int;
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reg output_udp_payload_tvalid_int;
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reg output_udp_payload_tready_int_reg = 1'b0;
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reg output_udp_payload_tlast_int;
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reg output_udp_payload_tuser_int;
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wire output_udp_payload_tready_int_early;
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assign input_ip_hdr_ready = input_ip_hdr_ready_reg;
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assign input_ip_payload_tready = input_ip_payload_tready_reg;
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assign output_udp_hdr_valid = output_udp_hdr_valid_reg;
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assign output_eth_dest_mac = output_eth_dest_mac_reg;
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assign output_eth_src_mac = output_eth_src_mac_reg;
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assign output_eth_type = output_eth_type_reg;
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assign output_ip_version = output_ip_version_reg;
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assign output_ip_ihl = output_ip_ihl_reg;
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assign output_ip_dscp = output_ip_dscp_reg;
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assign output_ip_ecn = output_ip_ecn_reg;
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assign output_ip_length = output_ip_length_reg;
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assign output_ip_identification = output_ip_identification_reg;
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assign output_ip_flags = output_ip_flags_reg;
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assign output_ip_fragment_offset = output_ip_fragment_offset_reg;
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assign output_ip_ttl = output_ip_ttl_reg;
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assign output_ip_protocol = output_ip_protocol_reg;
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assign output_ip_header_checksum = output_ip_header_checksum_reg;
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assign output_ip_source_ip = output_ip_source_ip_reg;
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assign output_ip_dest_ip = output_ip_dest_ip_reg;
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assign output_udp_source_port = output_udp_source_port_reg;
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assign output_udp_dest_port = output_udp_dest_port_reg;
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assign output_udp_length = output_udp_length_reg;
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assign output_udp_checksum = output_udp_checksum_reg;
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assign busy = busy_reg;
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assign error_header_early_termination = error_header_early_termination_reg;
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assign error_payload_early_termination = error_payload_early_termination_reg;
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always @* begin
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state_next = STATE_IDLE;
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input_ip_hdr_ready_next = 1'b0;
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input_ip_payload_tready_next = 1'b0;
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store_ip_hdr = 1'b0;
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store_udp_source_port_0 = 1'b0;
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store_udp_source_port_1 = 1'b0;
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store_udp_dest_port_0 = 1'b0;
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store_udp_dest_port_1 = 1'b0;
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store_udp_length_0 = 1'b0;
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store_udp_length_1 = 1'b0;
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store_udp_checksum_0 = 1'b0;
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store_udp_checksum_1 = 1'b0;
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store_last_word = 1'b0;
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frame_ptr_next = frame_ptr_reg;
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output_udp_hdr_valid_next = output_udp_hdr_valid_reg & ~output_udp_hdr_ready;
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error_header_early_termination_next = 1'b0;
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error_payload_early_termination_next = 1'b0;
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output_udp_payload_tdata_int = 8'd0;
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output_udp_payload_tvalid_int = 1'b0;
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output_udp_payload_tlast_int = 1'b0;
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output_udp_payload_tuser_int = 1'b0;
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case (state_reg)
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STATE_IDLE: begin
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// idle state - wait for header
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frame_ptr_next = 16'd0;
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input_ip_hdr_ready_next = ~output_udp_hdr_valid_reg;
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if (input_ip_hdr_ready & input_ip_hdr_valid) begin
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input_ip_hdr_ready_next = 1'b0;
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input_ip_payload_tready_next = 1'b1;
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store_ip_hdr = 1'b1;
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state_next = STATE_READ_HEADER;
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end else begin
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state_next = STATE_IDLE;
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end
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end
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STATE_READ_HEADER: begin
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// read header state
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input_ip_payload_tready_next = 1'b1;
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if (input_ip_payload_tready & input_ip_payload_tvalid) begin
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// word transfer in - store it
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frame_ptr_next = frame_ptr_reg + 16'd1;
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state_next = STATE_READ_HEADER;
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case (frame_ptr_reg)
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8'h00: store_udp_source_port_1 = 1'b1;
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8'h01: store_udp_source_port_0 = 1'b1;
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8'h02: store_udp_dest_port_1 = 1'b1;
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8'h03: store_udp_dest_port_0 = 1'b1;
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8'h04: store_udp_length_1 = 1'b1;
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8'h05: store_udp_length_0 = 1'b1;
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8'h06: store_udp_checksum_1 = 1'b1;
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8'h07: begin
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store_udp_checksum_0 = 1'b1;
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output_udp_hdr_valid_next = 1'b1;
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input_ip_payload_tready_next = output_udp_payload_tready_int_early;
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state_next = STATE_READ_PAYLOAD;
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end
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endcase
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if (input_ip_payload_tlast) begin
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error_header_early_termination_next = 1'b1;
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output_udp_hdr_valid_next = 1'b0;
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input_ip_hdr_ready_next = ~output_udp_hdr_valid_reg;
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input_ip_payload_tready_next = 1'b0;
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state_next = STATE_IDLE;
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end
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end else begin
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state_next = STATE_READ_HEADER;
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end
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end
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STATE_READ_PAYLOAD: begin
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// read payload
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input_ip_payload_tready_next = output_udp_payload_tready_int_early;
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output_udp_payload_tdata_int = input_ip_payload_tdata;
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output_udp_payload_tvalid_int = input_ip_payload_tvalid;
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output_udp_payload_tlast_int = input_ip_payload_tlast;
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output_udp_payload_tuser_int = input_ip_payload_tuser;
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if (input_ip_payload_tready & input_ip_payload_tvalid) begin
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// word transfer through
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frame_ptr_next = frame_ptr_reg + 16'd1;
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if (input_ip_payload_tlast) begin
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if (frame_ptr_next != output_udp_length_reg) begin
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// end of frame, but length does not match
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output_udp_payload_tuser_int = 1'b1;
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error_payload_early_termination_next = 1'b1;
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end
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input_ip_hdr_ready_next = ~output_udp_hdr_valid_reg;
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input_ip_payload_tready_next = 1'b0;
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state_next = STATE_IDLE;
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end else begin
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if (frame_ptr_next == output_udp_length_reg) begin
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store_last_word = 1'b1;
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output_udp_payload_tvalid_int = 1'b0;
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state_next = STATE_READ_PAYLOAD_LAST;
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end else begin
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state_next = STATE_READ_PAYLOAD;
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end
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end
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end else begin
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state_next = STATE_READ_PAYLOAD;
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end
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end
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STATE_READ_PAYLOAD_LAST: begin
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// read and discard until end of frame
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input_ip_payload_tready_next = output_udp_payload_tready_int_early;
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output_udp_payload_tdata_int = last_word_data_reg;
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output_udp_payload_tvalid_int = input_ip_payload_tvalid & input_ip_payload_tlast;
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output_udp_payload_tlast_int = input_ip_payload_tlast;
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output_udp_payload_tuser_int = input_ip_payload_tuser;
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if (input_ip_payload_tready & input_ip_payload_tvalid) begin
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if (input_ip_payload_tlast) begin
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input_ip_hdr_ready_next = ~output_udp_hdr_valid_reg;
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input_ip_payload_tready_next = 1'b0;
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state_next = STATE_IDLE;
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end else begin
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state_next = STATE_READ_PAYLOAD_LAST;
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end
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end else begin
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state_next = STATE_READ_PAYLOAD_LAST;
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end
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end
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STATE_WAIT_LAST: begin
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// wait for end of frame; read and discard
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input_ip_payload_tready_next = 1'b1;
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if (input_ip_payload_tready & input_ip_payload_tvalid) begin
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if (input_ip_payload_tlast) begin
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input_ip_hdr_ready_next = ~output_udp_hdr_valid_reg;
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input_ip_payload_tready_next = 1'b0;
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state_next = STATE_IDLE;
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end else begin
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state_next = STATE_WAIT_LAST;
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end
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end else begin
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state_next = STATE_WAIT_LAST;
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end
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end
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endcase
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end
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always @(posedge clk) begin
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if (rst) begin
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state_reg <= STATE_IDLE;
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frame_ptr_reg <= 16'd0;
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input_ip_hdr_ready_reg <= 1'b0;
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input_ip_payload_tready_reg <= 1'b0;
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output_udp_hdr_valid_reg <= 1'b0;
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busy_reg <= 1'b0;
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error_header_early_termination_reg <= 1'b0;
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error_payload_early_termination_reg <= 1'b0;
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end else begin
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state_reg <= state_next;
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frame_ptr_reg <= frame_ptr_next;
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input_ip_hdr_ready_reg <= input_ip_hdr_ready_next;
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input_ip_payload_tready_reg <= input_ip_payload_tready_next;
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output_udp_hdr_valid_reg <= output_udp_hdr_valid_next;
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error_header_early_termination_reg <= error_header_early_termination_next;
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error_payload_early_termination_reg <= error_payload_early_termination_next;
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busy_reg <= state_next != STATE_IDLE;
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end
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// datapath
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if (store_ip_hdr) begin
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output_eth_dest_mac_reg <= input_eth_dest_mac;
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output_eth_src_mac_reg <= input_eth_src_mac;
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output_eth_type_reg <= input_eth_type;
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output_ip_version_reg <= input_ip_version;
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output_ip_ihl_reg <= input_ip_ihl;
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output_ip_dscp_reg <= input_ip_dscp;
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output_ip_ecn_reg <= input_ip_ecn;
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output_ip_length_reg <= input_ip_length;
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output_ip_identification_reg <= input_ip_identification;
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output_ip_flags_reg <= input_ip_flags;
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output_ip_fragment_offset_reg <= input_ip_fragment_offset;
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output_ip_ttl_reg <= input_ip_ttl;
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output_ip_protocol_reg <= input_ip_protocol;
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output_ip_header_checksum_reg <= input_ip_header_checksum;
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output_ip_source_ip_reg <= input_ip_source_ip;
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output_ip_dest_ip_reg <= input_ip_dest_ip;
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end
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if (store_last_word) begin
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last_word_data_reg <= output_udp_payload_tdata_int;
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end
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if (store_udp_source_port_0) output_udp_source_port_reg[ 7: 0] <= input_ip_payload_tdata;
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if (store_udp_source_port_1) output_udp_source_port_reg[15: 8] <= input_ip_payload_tdata;
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if (store_udp_dest_port_0) output_udp_dest_port_reg[ 7: 0] <= input_ip_payload_tdata;
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if (store_udp_dest_port_1) output_udp_dest_port_reg[15: 8] <= input_ip_payload_tdata;
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if (store_udp_length_0) output_udp_length_reg[ 7: 0] <= input_ip_payload_tdata;
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if (store_udp_length_1) output_udp_length_reg[15: 8] <= input_ip_payload_tdata;
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if (store_udp_checksum_0) output_udp_checksum_reg[ 7: 0] <= input_ip_payload_tdata;
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if (store_udp_checksum_1) output_udp_checksum_reg[15: 8] <= input_ip_payload_tdata;
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end
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// output datapath logic
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reg [7:0] output_udp_payload_tdata_reg = 8'd0;
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reg output_udp_payload_tvalid_reg = 1'b0, output_udp_payload_tvalid_next;
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reg output_udp_payload_tlast_reg = 1'b0;
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reg output_udp_payload_tuser_reg = 1'b0;
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reg [7:0] temp_udp_payload_tdata_reg = 8'd0;
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reg temp_udp_payload_tvalid_reg = 1'b0, temp_udp_payload_tvalid_next;
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reg temp_udp_payload_tlast_reg = 1'b0;
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reg temp_udp_payload_tuser_reg = 1'b0;
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// datapath control
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reg store_udp_payload_int_to_output;
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reg store_udp_payload_int_to_temp;
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reg store_udp_payload_temp_to_output;
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assign output_udp_payload_tdata = output_udp_payload_tdata_reg;
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assign output_udp_payload_tvalid = output_udp_payload_tvalid_reg;
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assign output_udp_payload_tlast = output_udp_payload_tlast_reg;
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assign output_udp_payload_tuser = output_udp_payload_tuser_reg;
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// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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assign output_udp_payload_tready_int_early = output_udp_payload_tready | (~temp_udp_payload_tvalid_reg & (~output_udp_payload_tvalid_reg | ~output_udp_payload_tvalid_int));
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always @* begin
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// transfer sink ready state to source
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output_udp_payload_tvalid_next = output_udp_payload_tvalid_reg;
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temp_udp_payload_tvalid_next = temp_udp_payload_tvalid_reg;
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|
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store_udp_payload_int_to_output = 1'b0;
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store_udp_payload_int_to_temp = 1'b0;
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store_udp_payload_temp_to_output = 1'b0;
|
|
|
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if (output_udp_payload_tready_int_reg) begin
|
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// input is ready
|
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if (output_udp_payload_tready | ~output_udp_payload_tvalid_reg) begin
|
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// output is ready or currently not valid, transfer data to output
|
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output_udp_payload_tvalid_next = output_udp_payload_tvalid_int;
|
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store_udp_payload_int_to_output = 1'b1;
|
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end else begin
|
|
// output is not ready, store input in temp
|
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temp_udp_payload_tvalid_next = output_udp_payload_tvalid_int;
|
|
store_udp_payload_int_to_temp = 1'b1;
|
|
end
|
|
end else if (output_udp_payload_tready) begin
|
|
// input is not ready, but output is ready
|
|
output_udp_payload_tvalid_next = temp_udp_payload_tvalid_reg;
|
|
temp_udp_payload_tvalid_next = 1'b0;
|
|
store_udp_payload_temp_to_output = 1'b1;
|
|
end
|
|
end
|
|
|
|
always @(posedge clk) begin
|
|
if (rst) begin
|
|
output_udp_payload_tvalid_reg <= 1'b0;
|
|
output_udp_payload_tready_int_reg <= 1'b0;
|
|
temp_udp_payload_tvalid_reg <= 1'b0;
|
|
end else begin
|
|
output_udp_payload_tvalid_reg <= output_udp_payload_tvalid_next;
|
|
output_udp_payload_tready_int_reg <= output_udp_payload_tready_int_early;
|
|
temp_udp_payload_tvalid_reg <= temp_udp_payload_tvalid_next;
|
|
end
|
|
|
|
// datapath
|
|
if (store_udp_payload_int_to_output) begin
|
|
output_udp_payload_tdata_reg <= output_udp_payload_tdata_int;
|
|
output_udp_payload_tlast_reg <= output_udp_payload_tlast_int;
|
|
output_udp_payload_tuser_reg <= output_udp_payload_tuser_int;
|
|
end else if (store_udp_payload_temp_to_output) begin
|
|
output_udp_payload_tdata_reg <= temp_udp_payload_tdata_reg;
|
|
output_udp_payload_tlast_reg <= temp_udp_payload_tlast_reg;
|
|
output_udp_payload_tuser_reg <= temp_udp_payload_tuser_reg;
|
|
end
|
|
|
|
if (store_udp_payload_int_to_temp) begin
|
|
temp_udp_payload_tdata_reg <= output_udp_payload_tdata_int;
|
|
temp_udp_payload_tlast_reg <= output_udp_payload_tlast_int;
|
|
temp_udp_payload_tuser_reg <= output_udp_payload_tuser_int;
|
|
end
|
|
end
|
|
|
|
endmodule
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