mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-28 07:03:08 +08:00
249 lines
6.7 KiB
Python
249 lines
6.7 KiB
Python
#!/usr/bin/env python
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"""
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Copyright (c) 2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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import itertools
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import logging
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import os
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import cocotb_test.simulator
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import pytest
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import RisingEdge
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from cocotb.regression import TestFactory
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from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
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def cobs_encode(block):
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block = bytearray(block)
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enc = bytearray()
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seg = bytearray()
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code = 1
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new_data = True
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for b in block:
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if b == 0:
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enc.append(code)
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enc.extend(seg)
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code = 1
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seg = bytearray()
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new_data = True
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else:
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code += 1
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seg.append(b)
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new_data = True
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if code == 255:
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enc.append(code)
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enc.extend(seg)
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code = 1
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seg = bytearray()
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new_data = False
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if new_data:
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enc.append(code)
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enc.extend(seg)
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return bytes(enc)
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def cobs_decode(block):
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block = bytearray(block)
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dec = bytearray()
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code = 0
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i = 0
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if 0 in block:
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return None
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while i < len(block):
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code = block[i]
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i += 1
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if i+code-1 > len(block):
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return None
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dec.extend(block[i:i+code-1])
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i += code-1
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if code < 255 and i < len(block):
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dec.append(0)
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return bytes(dec)
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def prbs31(state=0x7fffffff):
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while True:
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for i in range(8):
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if bool(state & 0x08000000) ^ bool(state & 0x40000000):
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state = ((state & 0x3fffffff) << 1) | 1
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else:
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state = (state & 0x3fffffff) << 1
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yield state & 0xff
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class TB(object):
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def __init__(self, dut):
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self.dut = dut
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self.log = logging.getLogger("cocotb.tb")
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self.log.setLevel(logging.DEBUG)
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cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
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self.source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "s_axis"), dut.clk, dut.rst)
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self.sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "m_axis"), dut.clk, dut.rst)
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def set_idle_generator(self, generator=None):
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if generator:
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self.source.set_pause_generator(generator())
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def set_backpressure_generator(self, generator=None):
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if generator:
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self.sink.set_pause_generator(generator())
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async def reset(self):
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self.dut.rst.setimmediatevalue(0)
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 1
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 0
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
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tb = TB(dut)
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append_zero = int(os.getenv("PARAM_APPEND_ZERO"))
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await tb.reset()
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tb.set_idle_generator(idle_inserter)
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tb.set_backpressure_generator(backpressure_inserter)
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test_frames = [payload_data(x) for x in payload_lengths()]
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for test_data in test_frames:
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test_frame = AxiStreamFrame(test_data)
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await tb.source.send(test_frame)
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for test_data in test_frames:
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rx_frame = await tb.sink.recv()
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if append_zero:
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assert rx_frame.tdata == cobs_encode(test_data)+b'\x00'
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assert cobs_decode(rx_frame.tdata[:-1]) == test_data
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else:
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assert rx_frame.tdata == cobs_encode(test_data)
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assert cobs_decode(rx_frame.tdata) == test_data
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assert not rx_frame.tuser
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assert tb.sink.empty()
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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def cycle_pause():
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return itertools.cycle([1, 1, 1, 0])
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def size_list():
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return list(range(1, 33))+list(range(253, 259))+[512]+[1]*64
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def zero_payload(length):
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return bytearray(length)
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def incrementing_payload(length):
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return bytearray(itertools.islice(itertools.cycle(range(256)), length))
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def nonzero_incrementing_payload(length):
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return bytearray(itertools.islice(itertools.cycle(range(1, 256)), length))
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def nonzero_incrementing_payload_zero_framed(length):
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return bytearray([0]+list(itertools.islice(itertools.cycle(range(1, 256)), length))+[0])
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def prbs_payload(length):
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gen = prbs31()
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return bytearray([next(gen) for x in range(length)])
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if cocotb.SIM_NAME:
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factory = TestFactory(run_test)
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factory.add_option("payload_lengths", [size_list])
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factory.add_option("payload_data", [zero_payload, nonzero_incrementing_payload, nonzero_incrementing_payload_zero_framed, prbs_payload])
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factory.add_option("idle_inserter", [None, cycle_pause])
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factory.add_option("backpressure_inserter", [None, cycle_pause])
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factory.generate_tests()
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# cocotb-test
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tests_dir = os.path.dirname(__file__)
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rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
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@pytest.mark.parametrize("append_zero", [0, 1])
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def test_axis_cobs_encode(request, append_zero):
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dut = "axis_cobs_encode"
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module = os.path.splitext(os.path.basename(__file__))[0]
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toplevel = dut
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verilog_sources = [
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os.path.join(rtl_dir, f"{dut}.v"),
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os.path.join(rtl_dir, "axis_fifo.v"),
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]
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parameters = {}
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parameters['APPEND_ZERO'] = append_zero
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extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
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sim_build = os.path.join(tests_dir, "sim_build",
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request.node.name.replace('[', '-').replace(']', ''))
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cocotb_test.simulator.run(
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python_search=[tests_dir],
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verilog_sources=verilog_sources,
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toplevel=toplevel,
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module=module,
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parameters=parameters,
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sim_build=sim_build,
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extra_env=extra_env,
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)
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