FPGA/verilog-ethernet
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verilog-ethernet/example
History
Alex Forencich 9e44987f60 Reorganize PHY instances
2021-11-02 23:30:48 -07:00
..
ADM_PCIE_9V3
Add missing PHY instance ports
2021-11-02 20:28:26 -07:00
Arty/fpga
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
ATLYS/fpga
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
AU50/fpga_10g
Add missing PHY instance ports
2021-11-02 20:28:26 -07:00
AU200/fpga_10g
Add missing PHY instance ports
2021-11-02 20:28:26 -07:00
AU250/fpga_10g
Add missing PHY instance ports
2021-11-02 20:28:26 -07:00
AU280/fpga_10g
Add missing PHY instance ports
2021-11-02 20:28:26 -07:00
C10LP/fpga
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
DE2-115/fpga
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
DE5-Net/fpga
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
ExaNIC_X10/fpga
Add missing PHY instance ports
2021-11-02 20:28:26 -07:00
ExaNIC_X25/fpga_10g
Add missing PHY instance ports
2021-11-02 20:28:26 -07:00
fb2CG/fpga_10g
Add missing PHY instance ports
2021-11-02 20:28:26 -07:00
HTG9200/fpga_10g
Add missing PHY instance ports
2021-11-02 20:28:26 -07:00
HXT100G
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
KC705
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
ML605
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
NetFPGA_SUME/fpga
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
NexysVideo/fpga
Add default_nettype none and resetall directives
2021-10-20 17:29:12 -07:00
S10DX_DK/fpga_10g
Update QSF/SDC files
2021-11-02 23:30:06 -07:00
S10MX_DK/fpga_10g
Reorganize PHY instances
2021-11-02 23:30:48 -07:00
VCU108
Add missing PHY instance ports
2021-11-02 20:28:26 -07:00
VCU118
Add missing PHY instance ports
2021-11-02 20:28:26 -07:00
VCU1525/fpga_10g
Add missing PHY instance ports
2021-11-02 20:28:26 -07:00
ZCU102/fpga
Add missing PHY instance ports
2021-11-02 20:28:26 -07:00
ZCU106/fpga
Add missing PHY instance ports
2021-11-02 20:28:26 -07:00