mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-14 06:43:18 +08:00
247 lines
6.1 KiB
Python
Executable File
247 lines
6.1 KiB
Python
Executable File
#!/usr/bin/env python
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"""
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Copyright (c) 2019 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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from myhdl import *
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import os
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import ptp
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module = 'ptp_clock_cdc'
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testbench = 'test_%s_96' % module
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srcs = []
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srcs.append("../rtl/%s.v" % module)
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srcs.append("%s.v" % testbench)
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src = ' '.join(srcs)
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build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
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def bench():
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# Parameters
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TS_WIDTH = 96
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NS_WIDTH = 4
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FNS_WIDTH = 16
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INPUT_PERIOD_NS = 0x6
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INPUT_PERIOD_FNS = 0x6666
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OUTPUT_PERIOD_NS = 0x6
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OUTPUT_PERIOD_FNS = 0x6666
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USE_SAMPLE_CLOCK = 1
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LOG_FIFO_DEPTH = 3
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LOG_RATE = 3
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# Inputs
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clk = Signal(bool(0))
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rst = Signal(bool(0))
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current_test = Signal(intbv(0)[8:])
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input_clk = Signal(bool(0))
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input_rst = Signal(bool(0))
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output_clk = Signal(bool(0))
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output_rst = Signal(bool(0))
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sample_clk = Signal(bool(0))
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input_ts = Signal(intbv(0)[96:])
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# Outputs
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output_ts = Signal(intbv(0)[96:])
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output_ts_step = Signal(bool(0))
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output_pps = Signal(bool(0))
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# PTP clock
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ptp_clock = ptp.PtpClock(period_ns=INPUT_PERIOD_NS, period_fns=INPUT_PERIOD_FNS)
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ptp_logic = ptp_clock.create_logic(
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input_clk,
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input_rst,
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ts_96=input_ts
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)
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# DUT
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if os.system(build_cmd):
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raise Exception("Error running build command")
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dut = Cosimulation(
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"vvp -m myhdl %s.vvp -lxt2" % testbench,
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clk=clk,
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rst=rst,
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current_test=current_test,
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input_clk=input_clk,
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input_rst=input_rst,
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output_clk=output_clk,
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output_rst=output_rst,
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sample_clk=sample_clk,
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input_ts=input_ts,
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output_ts=output_ts,
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output_ts_step=output_ts_step,
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output_pps=output_pps
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)
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@always(delay(3200))
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def clkgen():
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clk.next = not clk
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input_clk.next = not input_clk
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output_clk_hp = Signal(int(3200))
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@instance
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def clkgen_output():
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while True:
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yield delay(int(output_clk_hp))
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output_clk.next = not output_clk
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@always(delay(5000))
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def clkgen_sample():
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sample_clk.next = not sample_clk
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@instance
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def check():
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yield delay(100000)
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yield clk.posedge
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rst.next = 1
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input_rst.next = 1
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output_rst.next = 1
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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input_rst.next = 0
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output_rst.next = 0
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yield clk.posedge
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yield delay(100000)
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yield clk.posedge
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# testbench stimulus
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yield clk.posedge
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print("test 1: Same clock speed")
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current_test.next = 1
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yield clk.posedge
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for i in range(20000):
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yield clk.posedge
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input_stop_ts = input_ts[96:48] + (input_ts[48:0]/2**16*1e-9)
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output_stop_ts = output_ts[96:48] + (output_ts[48:0]/2**16*1e-9)
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print(input_stop_ts-output_stop_ts)
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assert abs(input_stop_ts-output_stop_ts) < 1e-8
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yield delay(100000)
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yield clk.posedge
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print("test 2: Slightly faster")
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current_test.next = 2
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output_clk_hp.next = 3100
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yield clk.posedge
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for i in range(20000):
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yield clk.posedge
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input_stop_ts = input_ts[96:48] + (input_ts[48:0]/2**16*1e-9)
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output_stop_ts = output_ts[96:48] + (output_ts[48:0]/2**16*1e-9)
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print(input_stop_ts-output_stop_ts)
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assert abs(input_stop_ts-output_stop_ts) < 1e-8
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yield delay(100000)
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yield clk.posedge
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print("test 3: Slightly slower")
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current_test.next = 3
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output_clk_hp.next = 3300
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yield clk.posedge
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for i in range(20000):
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yield clk.posedge
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input_stop_ts = input_ts[96:48] + (input_ts[48:0]/2**16*1e-9)
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output_stop_ts = output_ts[96:48] + (output_ts[48:0]/2**16*1e-9)
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print(input_stop_ts-output_stop_ts)
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assert abs(input_stop_ts-output_stop_ts) < 1e-8
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yield delay(100000)
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yield clk.posedge
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print("test 4: Significantly faster")
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current_test.next = 4
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output_clk_hp.next = 2000
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yield clk.posedge
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for i in range(20000):
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yield clk.posedge
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input_stop_ts = input_ts[96:48] + (input_ts[48:0]/2**16*1e-9)
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output_stop_ts = output_ts[96:48] + (output_ts[48:0]/2**16*1e-9)
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print(input_stop_ts-output_stop_ts)
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assert abs(input_stop_ts-output_stop_ts) < 1e-8
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yield delay(100000)
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yield clk.posedge
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print("test 5: Significantly slower")
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current_test.next = 5
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output_clk_hp.next = 5000
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yield clk.posedge
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for i in range(30000):
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yield clk.posedge
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input_stop_ts = input_ts[96:48] + (input_ts[48:0]/2**16*1e-9)
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output_stop_ts = output_ts[96:48] + (output_ts[48:0]/2**16*1e-9)
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print(input_stop_ts-output_stop_ts)
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assert abs(input_stop_ts-output_stop_ts) < 1e-8
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yield delay(100000)
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raise StopSimulation
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return instances()
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def test_bench():
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sim = Simulation(bench())
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sim.run()
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if __name__ == '__main__':
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print("Running test...")
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test_bench()
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