mirror of
https://github.com/alexforencich/verilog-ethernet.git
synced 2025-01-28 07:03:08 +08:00
69 lines
2.2 KiB
Makefile
69 lines
2.2 KiB
Makefile
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# FPGA settings
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FPGA_TOP = fpga
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FPGA_FAMILY = "Stratix 10 MX"
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FPGA_DEVICE = 1SM21BHU2F53E1VG
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# Files for synthesis
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SYN_FILES = rtl/fpga.v
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SYN_FILES += rtl/fpga_core.v
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SYN_FILES += rtl/sync_signal.v
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SYN_FILES += rtl/eth_xcvr_phy_wrapper.v
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SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v
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SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
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SYN_FILES += lib/eth/rtl/eth_mac_10g.v
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SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
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SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
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SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
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SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
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SYN_FILES += lib/eth/rtl/lfsr.v
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SYN_FILES += lib/eth/rtl/eth_axis_rx.v
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SYN_FILES += lib/eth/rtl/eth_axis_tx.v
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SYN_FILES += lib/eth/rtl/udp_complete_64.v
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SYN_FILES += lib/eth/rtl/udp_checksum_gen_64.v
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SYN_FILES += lib/eth/rtl/udp_64.v
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SYN_FILES += lib/eth/rtl/udp_ip_rx_64.v
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SYN_FILES += lib/eth/rtl/udp_ip_tx_64.v
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SYN_FILES += lib/eth/rtl/ip_complete_64.v
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SYN_FILES += lib/eth/rtl/ip_64.v
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SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v
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SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v
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SYN_FILES += lib/eth/rtl/ip_arb_mux.v
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SYN_FILES += lib/eth/rtl/arp.v
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SYN_FILES += lib/eth/rtl/arp_cache.v
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SYN_FILES += lib/eth/rtl/arp_eth_rx.v
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SYN_FILES += lib/eth/rtl/arp_eth_tx.v
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SYN_FILES += lib/eth/rtl/eth_arb_mux.v
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SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
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SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
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SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
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SYN_FILES += lib/eth/lib/axis/rtl/axis_register.v
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SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
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SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
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SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
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# IP files
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IP_TCL_FILES += ip/reset_release.tcl
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IP_TCL_FILES += ip/eth_xcvr.tcl
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IP_TCL_FILES += ip/eth_xcvr_pll.tcl
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IP_TCL_FILES += ip/eth_xcvr_reset.tcl
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# QSF files
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QSF_FILES = fpga.qsf
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# SDC files
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SDC_FILES = fpga.sdc
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include ../common/quartus_pro.mk
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program: fpga
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quartus_pgm --no_banner --mode=jtag -o "P;$(FPGA_TOP).sof@1"
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