FPGA/verilog-ethernet
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verilog-ethernet/rtl
History
Alex Forencich 786eabac4b Add missing wires
2021-10-20 02:01:33 -07:00
..
arp_cache.v
Implement ARP cache clear
2019-06-14 00:01:13 -07:00
arp_eth_rx.v
Parametrize ARP components
2020-02-20 16:49:47 -08:00
arp_eth_tx.v
Force tkeep output high if KEEP_ENABLE is false
2020-02-21 14:30:13 -08:00
arp.v
Fix broadcast address check
2021-08-08 13:25:39 -07:00
axis_baser_rx_64.v
Rewrite resets
2021-10-15 23:33:35 -07:00
axis_baser_tx_64.v
Rewrite resets
2021-10-15 23:33:35 -07:00
axis_eth_fcs_check_64.v
Rename ports
2018-11-07 22:35:06 -08:00
axis_eth_fcs_check.v
Rename ports
2018-11-07 22:35:06 -08:00
axis_eth_fcs_insert_64.v
Rename ports
2018-11-07 22:35:06 -08:00
axis_eth_fcs_insert.v
Rename ports
2018-11-07 22:35:06 -08:00
axis_eth_fcs.v
Assume tkeep[0] always high
2020-05-05 16:17:51 -07:00
axis_gmii_rx.v
Rewrite resets
2021-10-15 23:33:35 -07:00
axis_gmii_tx.v
Rewrite resets
2021-10-15 23:33:35 -07:00
axis_xgmii_rx_32.v
Rewrite resets
2021-10-15 23:33:35 -07:00
axis_xgmii_rx_64.v
Rewrite resets
2021-10-15 23:33:35 -07:00
axis_xgmii_tx_32.v
Rewrite resets
2021-10-15 23:33:35 -07:00
axis_xgmii_tx_64.v
Rewrite resets
2021-10-15 23:33:35 -07:00
eth_arb_mux.v
Remove string parameters
2021-06-02 17:50:26 -07:00
eth_axis_rx.v
Add missing reset
2020-02-23 17:18:59 -08:00
eth_axis_tx.v
Parametrize Ethernet frame parsing
2020-02-21 21:37:57 -08:00
eth_demux.v
Convert generated eth_demux to verilog parametrized module
2018-11-02 00:23:31 -07:00
eth_mac_1g_fifo.v
Update MAC modules for changes in FIFO modules
2021-08-26 00:55:12 -07:00
eth_mac_1g_gmii_fifo.v
Update MAC modules for changes in FIFO modules
2021-08-26 00:55:12 -07:00
eth_mac_1g_gmii.v
Prevent SRL inference in synchronizers
2019-03-28 12:36:32 -07:00
eth_mac_1g_rgmii_fifo.v
Update MAC modules for changes in FIFO modules
2021-08-26 00:55:12 -07:00
eth_mac_1g_rgmii.v
Use BUFG instead of BUFIO2 for DDR input on Spartan 6
2021-07-31 12:45:38 -07:00
eth_mac_1g.v
Decouple transmit PTP tag enable and transmit PTP timestamp enable
2019-06-09 22:03:24 -07:00
eth_mac_10g_fifo.v
Transfer PTP information in tuser
2021-09-01 15:56:00 -07:00
eth_mac_10g.v
Transfer PTP information in tuser
2021-09-01 15:56:00 -07:00
eth_mac_mii_fifo.v
Update MAC modules for changes in FIFO modules
2021-08-26 00:55:12 -07:00
eth_mac_mii.v
Add MII PHY interface, MAC wrappers, and testbenches
2019-03-28 19:18:03 -07:00
eth_mac_phy_10g_fifo.v
Add missing wires
2021-10-20 02:01:33 -07:00
eth_mac_phy_10g_rx.v
Rework PHY bitslip timing
2021-05-05 00:35:43 -07:00
eth_mac_phy_10g_tx.v
Remove extraneous code
2019-08-05 13:27:12 -07:00
eth_mac_phy_10g.v
Rework PHY bitslip timing
2021-05-05 00:35:43 -07:00
eth_mux.v
Convert generated eth_mux to verilog parametrized module
2018-10-31 15:48:12 -07:00
eth_phy_10g_rx_ber_mon.v
Init and reset to same value
2021-10-17 02:13:14 -07:00
eth_phy_10g_rx_frame_sync.v
Rework PHY bitslip timing
2021-05-05 00:35:43 -07:00
eth_phy_10g_rx_if.v
Add transceiver reset watchdog
2021-10-17 20:19:04 -07:00
eth_phy_10g_rx_watchdog.v
Add transceiver reset watchdog
2021-10-17 20:19:04 -07:00
eth_phy_10g_rx.v
Add transceiver reset watchdog
2021-10-17 20:19:04 -07:00
eth_phy_10g_tx_if.v
Add configurable serdes pipeline register chain
2019-06-19 00:57:28 -07:00
eth_phy_10g_tx.v
Detect bad XGMII encodings in PHY TX
2021-10-16 00:50:48 -07:00
eth_phy_10g.v
Add transceiver reset watchdog
2021-10-17 20:19:04 -07:00
gmii_phy_if.v
Happy new year
2018-02-26 12:50:51 -08:00
iddr.v
Add documentation
2018-06-04 18:21:55 -07:00
ip_64.v
Rename ports
2018-11-07 22:35:06 -08:00
ip_arb_mux.v
Remove string parameters
2021-06-02 17:50:26 -07:00
ip_complete_64.v
Remove string parameters
2021-06-02 17:50:26 -07:00
ip_complete.v
Remove string parameters
2021-06-02 17:50:26 -07:00
ip_demux.v
Convert generated ip_demux to verilog parametrized module
2018-11-02 00:25:23 -07:00
ip_eth_rx_64.v
More critical path optimizations
2019-06-19 15:06:55 -07:00
ip_eth_rx.v
Rework pointer handling to improve timing
2019-06-16 23:53:26 -07:00
ip_eth_tx_64.v
More critical path optimizations
2019-06-19 15:06:55 -07:00
ip_eth_tx.v
Rework pointer handling to improve timing
2019-06-16 23:53:26 -07:00
ip_mux.v
Convert generated ip_mux to verilog parametrized module
2018-10-31 18:08:39 -07:00
ip.v
Rename ports
2018-11-07 22:35:06 -08:00
lfsr.v
Happy new year
2018-02-26 12:50:51 -08:00
mii_phy_if.v
Add MII PHY interface, MAC wrappers, and testbenches
2019-03-28 19:18:03 -07:00
oddr.v
Add documentation
2018-06-04 18:21:55 -07:00
ptp_clock_cdc.v
Prevent latch inference
2021-03-30 22:23:40 -07:00
ptp_clock.v
PTP clock period is always positive
2021-03-17 21:13:36 -07:00
ptp_perout.v
Refactor PTP period output, implement error output
2021-03-30 15:25:34 -07:00
ptp_tag_insert.v
Add PTP tag inserter module
2019-07-18 22:39:50 -07:00
ptp_ts_extract.v
Back out previous change
2019-07-15 18:09:14 -07:00
rgmii_phy_if.v
Use BUFG instead of BUFIO2 for DDR input on Spartan 6
2021-07-31 12:45:38 -07:00
ssio_ddr_in_diff.v
Use BUFG instead of BUFIO2 for DDR input on Spartan 6
2021-07-31 12:43:33 -07:00
ssio_ddr_in.v
Use BUFG instead of BUFIO2 for DDR input on Spartan 6
2021-07-31 12:43:33 -07:00
ssio_ddr_out_diff.v
Happy new year
2018-02-26 12:50:51 -08:00
ssio_ddr_out.v
Happy new year
2018-02-26 12:50:51 -08:00
ssio_sdr_in_diff.v
Happy new year
2018-02-26 12:50:51 -08:00
ssio_sdr_in.v
Happy new year
2018-02-26 12:50:51 -08:00
ssio_sdr_out_diff.v
Happy new year
2018-02-26 12:50:51 -08:00
ssio_sdr_out.v
Happy new year
2018-02-26 12:50:51 -08:00
udp_64.v
Update FIFO instances and update MACs to use combined FIFO adapter module
2019-07-18 16:25:49 -07:00
udp_arb_mux.v
Remove string parameters
2021-06-02 17:50:26 -07:00
udp_checksum_gen_64.v
Update FIFO instances and update MACs to use combined FIFO adapter module
2019-07-18 16:25:49 -07:00
udp_checksum_gen.v
Update FIFO instances and update MACs to use combined FIFO adapter module
2019-07-18 16:25:49 -07:00
udp_complete_64.v
Remove string parameters
2021-06-02 17:50:26 -07:00
udp_complete.v
Remove string parameters
2021-06-02 17:50:26 -07:00
udp_demux.v
Convert generated udp_demux to verilog parametrized module
2018-11-02 00:39:52 -07:00
udp_ip_rx_64.v
More critical path optimizations
2019-06-19 15:06:55 -07:00
udp_ip_rx.v
Rework pointer handling to improve timing
2019-06-16 23:53:26 -07:00
udp_ip_tx_64.v
More critical path optimizations
2019-06-19 15:06:55 -07:00
udp_ip_tx.v
Rework pointer handling to improve timing
2019-06-16 23:53:26 -07:00
udp_mux.v
Convert generated udp_mux to verilog parametrized module
2018-10-31 18:09:44 -07:00
udp.v
Update FIFO instances and update MACs to use combined FIFO adapter module
2019-07-18 16:25:49 -07:00
xgmii_baser_dec_64.v
Unconditionally pass through ordered set data to simplify decode logic
2021-10-16 01:25:48 -07:00
xgmii_baser_enc_64.v
Detect bad XGMII encodings in PHY TX
2021-10-16 00:50:48 -07:00
xgmii_deinterleave.v
Happy new year
2018-02-26 12:50:51 -08:00
xgmii_interleave.v
Happy new year
2018-02-26 12:50:51 -08:00