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verilog-ethernet/rtl
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Alex Forencich a29282cdda Remove stall cycle in axis_arb_mux 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2024-01-17 15:08:57 -08:00
..
arbiter.v
Rewrite resets
2022-05-13 12:57:41 -07:00
axis_adapter.v
Rewrite width converter to reduce resource consumption
2023-08-14 16:56:54 -07:00
axis_arb_mux_wrap.py
Round up default KEEP_WIDTH settings when DATA_WIDTH is not a multiple of 8
2022-03-30 16:02:17 -07:00
axis_arb_mux.v
Remove stall cycle in axis_arb_mux
2024-01-17 15:08:57 -08:00
axis_async_fifo_adapter.v
Implement MARK_WHEN_FULL option in FIFOs
2023-08-16 12:50:12 -07:00
axis_async_fifo.v
Fix FIFO output pause logic
2024-01-17 12:17:11 -08:00
axis_broadcast_wrap.py
Round up default KEEP_WIDTH settings when DATA_WIDTH is not a multiple of 8
2022-03-30 16:02:17 -07:00
axis_broadcast.v
Revert change to early ready conditions for improved throughput
2022-09-18 12:07:11 -07:00
axis_cobs_decode.v
Revert change to early ready conditions for improved throughput
2022-09-18 12:07:11 -07:00
axis_cobs_encode.v
Revert change to early ready conditions for improved throughput
2022-09-18 12:07:11 -07:00
axis_crosspoint_wrap.py
Round up default KEEP_WIDTH settings when DATA_WIDTH is not a multiple of 8
2022-03-30 16:02:17 -07:00
axis_crosspoint.v
Rewrite resets
2022-05-13 12:57:41 -07:00
axis_demux_wrap.py
Round up default KEEP_WIDTH settings when DATA_WIDTH is not a multiple of 8
2022-03-30 16:02:17 -07:00
axis_demux.v
Revert change to early ready conditions for improved throughput
2022-09-18 12:07:11 -07:00
axis_fifo_adapter.v
Implement MARK_WHEN_FULL option in FIFOs
2023-08-16 12:50:12 -07:00
axis_fifo.v
Fix FIFO output pause logic
2024-01-17 12:17:11 -08:00
axis_frame_join_wrap.py
Add default_nettype none and resetall directives
2021-10-20 15:33:38 -07:00
axis_frame_join.v
Revert change to early ready conditions for improved throughput
2022-09-18 12:07:11 -07:00
axis_frame_len.v
Round up default KEEP_WIDTH settings when DATA_WIDTH is not a multiple of 8
2022-03-30 16:02:17 -07:00
axis_frame_length_adjust_fifo.v
Round up default KEEP_WIDTH settings when DATA_WIDTH is not a multiple of 8
2022-03-30 16:02:17 -07:00
axis_frame_length_adjust.v
Revert change to early ready conditions for improved throughput
2022-09-18 12:07:11 -07:00
axis_ll_bridge.v
Add default_nettype none and resetall directives
2021-10-20 15:33:38 -07:00
axis_mux_wrap.py
Round up default KEEP_WIDTH settings when DATA_WIDTH is not a multiple of 8
2022-03-30 16:02:17 -07:00
axis_mux.v
Revert change to early ready conditions for improved throughput
2022-09-18 12:07:11 -07:00
axis_pipeline_fifo.v
Reorganize pipeline FIFO to facilitate placement constraints
2023-07-27 01:43:36 -07:00
axis_pipeline_register.v
Round up default KEEP_WIDTH settings when DATA_WIDTH is not a multiple of 8
2022-03-30 16:02:17 -07:00
axis_ram_switch_wrap.py
Round up default KEEP_WIDTH settings when DATA_WIDTH is not a multiple of 8
2022-03-30 16:02:17 -07:00
axis_ram_switch.v
Round up default KEEP_WIDTH settings when DATA_WIDTH is not a multiple of 8
2022-03-30 16:02:17 -07:00
axis_rate_limit.v
Revert change to early ready conditions for improved throughput
2022-09-18 12:07:11 -07:00
axis_register.v
Revert change to early ready conditions for improved throughput
2022-09-18 12:07:11 -07:00
axis_srl_fifo.v
Rewrite resets
2022-05-13 12:57:41 -07:00
axis_srl_register.v
Rewrite resets
2022-05-13 12:57:41 -07:00
axis_stat_counter.v
Revert change to early ready conditions for improved throughput
2022-09-18 12:07:11 -07:00
axis_switch_wrap.py
Round up default KEEP_WIDTH settings when DATA_WIDTH is not a multiple of 8
2022-03-30 16:02:17 -07:00
axis_switch.v
Rewrite resets
2022-05-13 12:57:41 -07:00
axis_tap.v
Revert change to early ready conditions for improved throughput
2022-09-18 12:07:11 -07:00
ll_axis_bridge.v
Add default_nettype none and resetall directives
2021-10-20 15:33:38 -07:00
priority_encoder.v
Add default_nettype none and resetall directives
2021-10-20 15:33:38 -07:00
sync_reset.v
Add default_nettype none and resetall directives
2021-10-20 15:33:38 -07:00