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FPGA
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verilog-ethernet
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verilog-ethernet
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example
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ExaNIC_X10
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fpga
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rtl
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Alex Forencich
a55c354924
Parametrize Ethernet frame parsing
2020-02-21 21:37:57 -08:00
..
fpga_core.v
Parametrize Ethernet frame parsing
2020-02-21 21:37:57 -08:00
fpga.v
Switch out Xilinx PHY core in ExaNIC X10 example design
2019-01-18 13:49:46 -08:00
sync_reset.v
Add ExaNIC X10 example design
2019-01-08 17:22:01 -08:00
sync_signal.v
Add ExaNIC X10 example design
2019-01-08 17:22:01 -08:00
