FPGA/verilog-ethernet
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verilog-ethernet/example/VCU118/fpga_10g/rtl
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Alex Forencich a55c354924 Parametrize Ethernet frame parsing
2020-02-21 21:37:57 -08:00
..
debounce_switch.v
Add VCU118 10G example design
2018-06-13 19:30:07 -07:00
fpga_core.v
Parametrize Ethernet frame parsing
2020-02-21 21:37:57 -08:00
fpga.v
Use correct clock
2019-03-28 17:56:55 -07:00
mdio_master.v
Add VCU118 10G example design
2018-06-13 19:30:07 -07:00
sync_reset.v
Add VCU118 10G example design
2018-06-13 19:30:07 -07:00
sync_signal.v
Add VCU118 10G example design
2018-06-13 19:30:07 -07:00